This paper presents a novel dynamic latched comparator that demonstrates lower offset voltage and higher load drivability than the conventional dynamic latched comparators. With two additional inverters inserted between the input-and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage is improved. The complementary version of the regenerative latch stage, which provides larger output drive current than the conventional one at a limited area, is implemented. The proposed circuit is designed using 90nm CMOS technology and 1V power supply voltage, and it demonstrates up to 19% less offset voltage and 62% less sensitivity of the delay to the input voltage difference (17ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption.

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A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the inputreferred offset voltage of the latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption. In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 lW/GHz after calibration.

This paper proposes a novel approach to minimize leakage currents in CMOS circuits during the off-state (or standby mode, sleep mode) by applying the optimal reverse body bias to the substrate (body or bulk) to increase the threshold voltage of transistors. The optimal bias point is determined by comparing the sub-threshold current (I SUB ) and band-to-band current (I BTBT ) simultaneously. The proposed circuit was simulated in HSPICE using 32nm bulk CMOS technology and evaluated using ISCAS85 benchmark circuits at different operating temperature (ranging from 25 o C to 100 o C). Analysis of the results shows a maximum of 551 and 1491 times leakage power reduction at 25 o C and 100 o C on a circuit with 546 gates. The proposed approach demonstrates that the optimal body bias reduces considerable amount of the leakage power in the nanoscale CMOS integrated circuits. In this approach, the temperature and supply voltage variations are compensated by the proposed feedback loop.Keywords-off-state, standby mode, sleep mode, leakage currents, sub-threshold leakage current, band-to-band tunneling (BTBT) leakage current I.978-1-4244-3353-7/09/$25.00 ©2009 IEEE

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This paper presents a fully integrated on-chip switched-capacitor (SC) DC-DC converter that supports a programmable regulated power supply ranging from 2.6 to 3.2 V out of a 5 V input supply. The proposed 4-to-3 step-down topology utilizes two conventional 2-to-1 step-down topologies; each of them (2-to-1_up and 2-to-1_dw) has a different flying capacitance to maximize the load current driving capability while minimizing the bottom-plate capacitance loss. The control circuits use a low power supply provided by a small internal low-drop output (LDO) connected to the internal load voltage (V L_dw ) from the 2-to-1_dw, and low swing level-shifted gate-driving signals are generated using the internal load voltage (V L_dw ). Therefore, the proposed implementation reduces control circuit and switching power consumptions. The programmable power supply voltage is regulated by means of a pulse frequency modulation (PFM) technique with the compensated two-stage operational transconductance amplifier (OTA) and the current-starved voltage controlled oscillator (VCO) to maintain high efficiency over a wide range of load currents. The proposed on-chip SC DC-DC converter is designed and simulated using high-voltage 0.35 µm bipolar, complementary metal-oxide-semiconductor (CMOS) and DMOS (BCDMOS) technology. It achieves a peak efficiency of 74% when delivering an 8 mA load current at a 3.2 V supply voltage level, and it provides a maximum output power of 48 mW (I L = 15 mA at V L_up = 3.2 V) at 70.5% efficiency. The proposed on-chip SC voltage regulator shows better efficiency than the ideal linear regulator over a wide range of output power, from 2.6 mW to 48 mW. The 18-phase interleaving technique enables the worst-case output voltage ripple to be less than 5.77% of the load voltage.

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