A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator

Jeon, HeungJun; Kim, Yong-Bin

doi:10.1007/s10470-011-9687-5

Cited by 52 publications

(10 citation statements)

References 15 publications

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“…The regeneration speed affects the output settling time; the lower value of the proposed comparators thereby improves the operating frequency. The number of transistors, power consumption, and energy consumption is lower than [30], [31] and [32] but it is seen to be more than [29]. The kick-back noise is higher than [29], [30], [31] and [32], however its gets reduced with the sampling switch connected.…”

Section: A Performance Analysis Of Subranging Level Comparatorsmentioning

confidence: 92%

“…The number of transistors, power consumption, and energy consumption is lower than [30], [31] and [32] but it is seen to be more than [29]. The kick-back noise is higher than [29], [30], [31] and [32], however its gets reduced with the sampling switch connected. The kick-back noise is more without the sampling switch (worst case) and is around 0.84 mV, it gets reduced to 0.12 mV after using the sampling switch (best case) as it isolates the regeneration nodes during the evaluation phase of the comparison for the FCMP.…”

Section: A Performance Analysis Of Subranging Level Comparatorsmentioning

confidence: 92%

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Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

2019

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The sampling rate plays a key role in wireless applications at very high-frequency range. Flash analog-to-digital converter (ADC) betters the slow converter counterparts in this regard but bulky at inevitable high resolutions. A state-of-the-art Divide and Collate (DnC) algorithm is proposed to design the flash ADC at subranging levels. The offset voltage is kept at a minimum through the comparators used for novel coarse and fine conversion separately. The kick-back noise is also reduced by using sample and hold switches at the input. The 10-bit ADC architecture is designed with 45-nm CMOS technology and analyzed in the SPECTRE environment. A trivial variation in the transconductance with temperature is observed and consequently the offset drift with temperature is found to be 0.015 mV/ • C. The design improves the INL by 0.42 LSB and DNL by 0.3 LSB. Signal-tonoise-and-distortion (SNDR) ratio and spurious-free-dynamic-range (SFDR) are 51.8 dB and 62 dB respectively at a frequency range near the Nyquist rate with a supply voltage of 1 V and input frequency of 500 MHz. Subranging scheme minimizes the comparator requirements which is reflected in the 44% reduction in the power dissipation.

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Section: A Performance Analysis Of Subranging Level Comparatorsmentioning

confidence: 92%

Section: A Performance Analysis Of Subranging Level Comparatorsmentioning

confidence: 92%

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

2019

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“…In other words, it can be assumed that delay time always increases when the temperature increases. Theoretically, (15) also shows that the t o delay in the DT comparator is much more sensitive to temperature variations than in SA comparators.…”

Section: ) Strongarm Delaymentioning

confidence: 92%

A Temperature-Aware Analysis of SAR ADCs for Smart Vehicle Applications

Fonseca¹,

Ferreira²,

Cron³

et al. 2018

JICS

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The challenges of the Internet of Things (IoT) in an urban environment are driven by smart vehicles which need to be able to efficiently sense and communicate with other nearby vehicles. The automotive market have strict circuit performances and reliability requirements for a temperature range of up to 175 ◦C. This proposal overviews an analysis of latched-comparators performance, considering process variability and temperature variation of previous works. This analysis is then extended to the metastability and performance metrics of successive approximation register (SAR) analog-to-digital converter (ADC) topology. Building blocks necessary for the SAR ADC are designed using an XH018 technology. Post-layout simulation results are drawn to validate the proposed temperature-aware analysis. Besides the known advantages of the Double-Tail comparator, this work demonstrates that such a comparator has a serious drawback under harsh environments. This proposal also shows that, once calibrated and operated at a frequency of around 100 MHz, the SAR ADC performance can be maintained in a wide temperature range. Both SA- and DT-SAR ADC achieve an ENOB of 9.8 bits, which is reduced to 9.6 bits in high-temperature operation. The results also show that background calibration is not required for the SAR ADC operation at the 100 MHz frequency range.

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“…For the dynamic comparator, the offset voltage can be canceled through adjusting the load capacitance [9], the current [10], [11] or the threshold voltage of the differential pair.…”

Section: B Dynamic Comparator With Offset Cancellationmentioning

confidence: 99%

Asynchronous 10MS/s 10-Bit SAR ADC for Wireless Network

Zhang¹,

Guo²,

Yan³

et al. 2014

IJCTE

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Abstract-This paper presents a low power asynchronous 10-bit Successive Approximation Register (SAR) ADC implemented in 0.18μm CMOS process. The ADC is realized fully differentially with a split capacitor array to lower power cost and improve the speed. To further enhance power efficiency and high speed for a relatively moderate resolution, a new asynchronous dynamic logic is utilized to lower the digital power. The multiple-phase clock is generated by a ring-oscillator structure which avoids the high external clock. Offset of the dynamic clocked-comparator is also calibrated through adjusting the threshold voltage. The ADC consumes 500uw at Vdd=1.8v and 10M/s sampling rate.Index Terms-SAR analog to digital converter (ADC), low power, fully dynamic comparator, CMOS, offset cancellation, asynchronous logic.

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A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator

Cited by 52 publications

References 15 publications

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

A Temperature-Aware Analysis of SAR ADCs for Smart Vehicle Applications

Asynchronous 10MS/s 10-Bit SAR ADC for Wireless Network

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