Asynchronous 10MS/s 10-Bit SAR ADC for Wireless Network

Abstract

Abstract-This paper presents a low power asynchronous 10-bit Successive Approximation Register (SAR) ADC implemented in 0.18μm CMOS process. The ADC is realized fully differentially with a split capacitor array to lower power cost and improve the speed. To further enhance power efficiency and high speed for a relatively moderate resolution, a new asynchronous dynamic logic is utilized to lower the digital power. The multiple-phase clock is generated by a ring-oscillator structure which avoids the high external clock. Offset of the dynamic clocked-comparator is also calibrated through adjusting the threshold voltage. The ADC consumes 500uw at Vdd=1.8v and 10M/s sampling rate.Index Terms-SAR analog to digital converter (ADC), low power, fully dynamic comparator, CMOS, offset cancellation, asynchronous logic.

Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator

“…Additionally, a resistor is used to avoid the degradation in the phase margin. To overcome these issues, an indirect method of compensation has been adopted using split-length devices [19].…”

“…To overcome these issues, an indirect method of compensation has been adopted using split-length devices [19]. Figure 10 shows the simulation results of the reference voltage generator.…”