Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator

Shehzad, Khuram; Verma, Deeksha; Khan, Danial; Ain, Qurat ul; Basim, Muhammad; Kim, Sung Jin; Pu, YoungGun; Hwang, Keum Cheol; Yang, Youngoo; Lee, Kang-Yoon

doi:10.3390/electronics9050872

Cited by 13 publications

(12 citation statements)

References 24 publications

(30 reference statements)

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“…Table 1 presents different successive approximation register analog-to-digital converter results, including the SAR-ADC-WFC-CDA. In these papers, the power consumption which is less than 10 uW are [1], [2], [3], [5], while the SAR-ADC-WFC-CDA and the FOM of the SAR-ADC-WFC-CDA is lower than other papers. Table 1.…”

Section: Measurement and Discussionmentioning

confidence: 99%

“…The equations for the average switching energy of the SW-B-M are (11) and 341 Cu(VH) 2 . The switch numbers are 4n + 8, and the unit capacitor (Cu) number is 2 n−1 [9,10] The SAR-ADC-WFC-CDA uses a segmented method for the fine conversion CDAC and the non-binary weighted method for the course conversion CDAC.…”

Section: Analysis Of the Switching Base Vm (Sw-b-m) Algorithm And Arcmentioning

confidence: 99%

“…Figure 3 shows the SW-B-M architecture with the fine plus course conversion CDAC. The equations for the average switching energy of the SW-B-M are (11) and 341 Cu(VH) 2 . The switch numbers are 4n + 8, and the unit capacitor (Cu) number is 2 −1 [9,10].…”

Section: Non-binary Algorithmmentioning

confidence: 99%

“…Moreover, fully-synthesizable successive approximation register (SAR) analog-todigital converters (ADCs) were presented and the dyadic digital pulse modulation (DDPM) digital-to-analog (DAC) was used and FOM is higher than the traditional SAR-ADC [1]. An energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter was presented and the power consumption is 108 uW [2]. The method of the estimated lower bound to the power consumption of successive approximation analog-to-digital converters is presented [3] and FOM is 94.5 fJ/conversion.…”

Section: Introductionmentioning

confidence: 99%

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An Innovative Successive Approximation Register Analog-to-Digital Converter for a Nine-Axis Sensing System

Lin

Wen

2021

JLPEA

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With nine-axis sensing systems in 5G smartphones, mobile power consumption has become increasingly important, and ultra-low-power (ULP) sensor circuits can decrease power consumption to tens of microwatts. This paper presents an innovative successive approximation register analog-to-digital converter, which comprises fine (three most significant bits (MSBs) plus course conversion (11 least significant bits (LSBs)) capacitive digital-to-analog converters (CDACs), ULP, four-mode reconfigurable resolution (9, 10, 11, or 12 bits), an internally generated clock, meta-detection, the switching base midpoint voltage (Vm) (SW-B-M), bit control logic, multi-phase control logic, fine (three MSBs) plus course conversion (11 LSBs) switch control logic, phase control logic, and an input signal plus negative voltage (VI + NEG) voltage generator. Then, the mechanism of the discrete Fourier transform (DFT)-based calibration is applied. The scalable voltage technique was used, and the analog/digital voltage was Vanalog (1.5 V) and Vdigital (0.9 V) to meet the specifications of the nine-axis ULP sensing system. The CDACs can reconfigure four-mode resolutions, 9–12 bits, for use in nine-axis sensor applications. The corresponding dynamic signal-to-noise and distortion ratio performance was 50.78, 58.53, 62.42, and 66.51 dB. In the 12-bit mode, the power consumption of the ADC was approximately 2.7 μW, and the corresponding figure of merit (FoM) was approximately 30.5 fJ for each conversion step.

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Section: Measurement and Discussionmentioning

confidence: 99%

Section: Analysis Of the Switching Base Vm (Sw-b-m) Algorithm And Arcmentioning

confidence: 99%

Section: Non-binary Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An Innovative Successive Approximation Register Analog-to-Digital Converter for a Nine-Axis Sensing System

Lin

Wen

2021

JLPEA

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“…In the previous designs, successive approximation register (SAR) ADC has been used for this purpose due to its low power consumption. This ADC structure is not suitable for high-accuracy measurements as it has a limitation in terms of resolution [ 22 , 23 , 24 , 25 ]. A reconfigurable second-order SD-ADC is designed for automotive PRT sensor.…”

Section: Sigma-delta Analog-to-digital Convertermentioning

confidence: 99%

A Highly Accurate, Polynomial-Based Digital Temperature Compensation for Piezoresistive Pressure Sensor in 180 nm CMOS Technology

Ali

Asif

Shehzad

et al. 2020

Sensors

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Recently, piezoresistive-type (PRT) pressure sensors have been gaining attention in variety of applications due to their simplicity, low cost, miniature size and ruggedness. The electrical behavior of a pressure sensor is highly dependent on the temperature gradient which seriously degrades its reliability and reduces measurement accuracy. In this paper, polynomial-based adaptive digital temperature compensation is presented for automotive piezoresistive pressure sensor applications. The non-linear temperature dependency of a pressure sensor is accurately compensated for by incorporating opposite characteristics of the pressure sensor as a function of temperature. The compensation polynomial is fully implemented in a digital system and a scaling technique is introduced to enhance its accuracy. The resource sharing technique is adopted for minimizing controller area and power consumption. The negative temperature coefficient (NTC) instead of proportional to absolute temperature (PTAT) or complementary to absolute temperature (CTAT) is used as the temperature-sensing element since it offers the best temperature characteristics for grade 0 ambient temperature operating range according to the automotive electronics council (AEC) test qualification ACE-Q100. The shared structure approach uses an existing analog signal conditioning path, composed of a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC). For improving the accuracy over wide range of temperature, a high-resolution sigma-delta ADC is integrated. The measured temperature compensation accuracy is within ±0.068% with full scale when temperature varies from −40 °C to 150 °C according to ACE-Q100. It takes 37 µs to compute the temperature compensation with a clock frequency of 10 MHz. The proposed technique is integrated in an automotive pressure sensor signal conditioning chip using a 180 nm complementary metal–oxide–semiconductor (CMOS) process.

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A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration

et al. 2021

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A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time interleaved synchronous Successive Approximation Register (SAR) ADC. The proposed architecture with a shared 6-bit Flash ADC and time interleaved SAR ADC provides a power and area efficient high speed ADC. The proposed Time-skew calibration is implemented to minimize the discrepancy between the output of Flash ADC and SAR ADC's channels. To rectify the decision error of the Flash ADC and extract the time-skew information, 1-bit redundancy is included in the CDAC of the SAR conversion. The decision error between the Flash ADC and the SAR ADC is covered with designed redundancy and the mismatch between the ADCs is covered with the time-skew calibration. To reduce the offset mismatch between Flash and SAR ADC and within SAR ADCs, all comparators are calibrated to minimize their absolute offset by utilizing background offset calibration. The modified dynamic strong ARM comparator is used for flash ADC and dynamic latched comparator is used for SAR ADCs. For fine offset calibration and low power consumption, the comparator's offset calibration circuit is implemented. To reduce the kickback noise and enhance the overall energy efficiency for fast operation of SAR ADCs, rail-to-rail dynamic latch comparator with modified adaptive power control (APC) is implemented. The proposed ADC structure has been implemented in 130 nm CMOS process. The ADC has an effective number of bit (ENOB) of 10.97 bits while consuming 7.08 mW current consumption from the 1.2 V supply voltage.INDEX TERMS Adaptive Power Control (APC), Comparator offset calibration, Hybrid type time interleaved SAR ADC, Low power consumption, redundant capacitor, Time-skew calibration, and Timeskew error.

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Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator

Cited by 13 publications

References 24 publications

An Innovative Successive Approximation Register Analog-to-Digital Converter for a Nine-Axis Sensing System

An Innovative Successive Approximation Register Analog-to-Digital Converter for a Nine-Axis Sensing System

A Highly Accurate, Polynomial-Based Digital Temperature Compensation for Piezoresistive Pressure Sensor in 180 nm CMOS Technology

A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration

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