This paper presents a reconfigurable radio frequency to direct current (RF-DC) converter operating at 902 MHz frequency designed to efficiently harvest RF signals and convert into useable DC voltages for RF energy harvesting applications. The proposed scheme employs a dual-path, a series (lowpower) path and a parallel (high-power) path, to maintain high power conversion efficiency (PCE) over wide input power range. The dual-path is composed of two identical rectifier blocks utilizing internal threshold voltage cancellation (IVC) technique to efficiently compensate the threshold voltage of the transistors used as rectifying devices. An adaptive control circuit (ACC) consisting of a comparator, an inverter and three switches is used in the proposed scheme. The ACC activates the series path or the parallel path to maximize the harvested power based on the input power range. The proposed scheme is designed and fabricated in a 180 nm complementary metal-oxide semiconductor (CMOS) technology. The measurement results show that PCE of the proposed circuit is above 20% from −18 dBm to −5 dBm, maintaining 13-dB input power range with peak PCE of 33% at −8 dBm for 200 k load resistance. The proposed circuit demonstrates −20.2 dBm sensitivity across 1 M load resistance while producing 1 V output DC voltage. INDEX TERMS CMOS technology, dual path, power conversion efficiency, reconfigurable, RF-DC power converter, RF energy harvesting.

No abstract

This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CVREF2 switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.

A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.

No abstract