This paper presents a duty cycle-based, dual-mode simultaneous wireless information and power transceiver (SWIPT) for Internet of Things (IoT) devices in which a sensor node monitors the received power and adaptively controls the single-tone or multitone communication mode. An adaptive power-splitting (PS) ratio control scheme distributes the received radio frequency (RF) energy between the energy harvesting (EH) path and the information decoding (ID) path. The proposed SWIPT enables the self-powering of an ID transceiver above 20 dBm input power, leading to a battery-free network. The optimized PS ratio of 0.44 enables it to provide sufficient harvested energy for self-powering and energy-neutral operation of the ID transceiver. The ID transceiver can demodulate the amplitude-shift keying (ASK) and the binary phase-shift keying (BPSK) signals. Moreover, for low-input power level, a peak-to-average power ratio (PAPR) scheme based on multitone is also proposed for demodulation of the information-carrying RF signals. Due to the limited power, information is transmitted in uplink by backscatter modulation instead of RF signaling. To validate our proposed SWIPT architecture, a SWIPT printed circuit board (PCB) was designed with a multitone SWIPT board at 900 MHz. The demodulation of multitone by PAPR was verified separately on the PCB. Results showed the measured sensitivity of the SWIPT to be −7 dBm, and the measured peak power efficiency of the RF energy harvester was 69% at 20 dBm input power level. The power consumption of the injection-locked oscillator (ILO)-based phase detection path was 13.6 mW, and it could be supplied from the EH path when the input power level was high. The ID path could demodulate 4-ASK- and BPSK-modulated signals at the same time, thus receiving 3 bits from the demodulation process. Maximum data rate of 4 Mbps was achieved in the measurement.
Summary
This paper presents a 6‐bit 4 MS/s segmented successive approximation register analog‐to‐digital converter for Bluetooth low energy transceiver applications. To improve the linearity and reduce the switching power consumption, a segmented structure with new switching scheme is adopted in the capacitive digital‐to‐analog converter. The proposed switching sequence determines the MSBs according to the thermometer codes and skips some of the unnecessary steps while avoiding bubble errors. To ensure the common mode voltage remains comparatively steady, and to avoid employing power‐hungry common mode reference voltage circuits, each capacitor is divided into 2 identical small capacitors, connecting one of them to “high” and the other one to “low”. The switching sequence is straightforward, and a split capacitor with an integer value is applied, which almost halves the total number of capacitors while retaining the unit capacitor value intact. The prototype analog‐to‐digital converter is fabricated and measured in a 55‐nm (shrinked 65 nm) complementary metal‐oxide semiconductor process and achieves 5.48 to 5.92 Effective Number of Bits (ENOB) at a sampling frequency of 4 MS/s. The Signal to Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) for Nyquist input frequency are 34.79 and 40.03 dB, respectively. The current consumption is 4.8 μA from a 1.0‐V supply, which corresponds to the figure of merit of 26 fJ/conversion‐step. The total active area of the analog‐to‐digital converters for the I and Q paths of the receiver is 105 μm × 140 μm.
A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.
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