The challenges of the Internet of Things (IoT) in an urban environment are driven by smart vehicles which need to be able to efficiently sense and communicate with other nearby vehicles. The automotive market have strict circuit performances and reliability requirements for a temperature range of up to 175 ◦C. This proposal overviews an analysis of latched-comparators performance, considering process variability and temperature variation of previous works. This analysis is then extended to the metastability and performance metrics of successive approximation register (SAR) analog-to-digital converter (ADC) topology. Building blocks necessary for the SAR ADC are designed using an XH018 technology. Post-layout simulation results are drawn to validate the proposed temperature-aware analysis. Besides the known advantages of the Double-Tail comparator, this work demonstrates that such a comparator has a serious drawback under harsh environments. This proposal also shows that, once calibrated and operated at a frequency of around 100 MHz, the SAR ADC performance can be maintained in a wide temperature range. Both SA- and DT-SAR ADC achieve an ENOB of 9.8 bits, which is reduced to 9.6 bits in high-temperature operation. The results also show that background calibration is not required for the SAR ADC operation at the 100 MHz frequency range.
Comparators are a critical element of Analog-to-Digital converters (ADCs) intended to operate in a harsh environments such as the automotive. The influence of temperature on key comparator properties such as the delay must be well understood to maximize their speed. In this paper a Double-Tail latch analysis leads to an analytical expression for the delay to more accurately guide the design over a wide temperature range. The results given by this model agree well with spice postlayout simulation for a CMOS 0.18-µm SOI process, taking into consideration both process and temperature variations. To verify experimentally the correctness of the model we also propose a novel on-chip fully digital asynchronous architecture to measure the delay of the comparator, robust against extreme temperature variations.
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