Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

Abstract

The sampling rate plays a key role in wireless applications at very high-frequency range. Flash analog-to-digital converter (ADC) betters the slow converter counterparts in this regard but bulky at inevitable high resolutions. A state-of-the-art Divide and Collate (DnC) algorithm is proposed to design the flash ADC at subranging levels. The offset voltage is kept at a minimum through the comparators used for novel coarse and fine conversion separately. The kick-back noise is also reduced by using sample and hold switches at the input. The 10-bit ADC architecture is designed with 45-nm CMOS technology and analyzed in the SPECTRE environment. A trivial variation in the transconductance with temperature is observed and consequently the offset drift with temperature is found to be 0.015 mV/ • C. The design improves the INL by 0.42 LSB and DNL by 0.3 LSB. Signal-tonoise-and-distortion (SNDR) ratio and spurious-free-dynamic-range (SFDR) are 51.8 dB and 62 dB respectively at a frequency range near the Nyquist rate with a supply voltage of 1 V and input frequency of 500 MHz. Subranging scheme minimizes the comparator requirements which is reflected in the 44% reduction in the power dissipation.