A novel technique to minimize standby leakage power in nanoscale CMOS VLSI

Abstract

This paper proposes a novel approach to minimize leakage currents in CMOS circuits during the off-state (or standby mode, sleep mode) by applying the optimal reverse body bias to the substrate (body or bulk) to increase the threshold voltage of transistors. The optimal bias point is determined by comparing the sub-threshold current (I SUB ) and band-to-band current (I BTBT ) simultaneously. The proposed circuit was simulated in HSPICE using 32nm bulk CMOS technology and evaluated using ISCAS85 benchmark circuits at different operating temperature (ranging from 25 o C to 100 o C). Analysis of the results shows a maximum of 551 and 1491 times leakage power reduction at 25 o C and 100 o C on a circuit with 546 gates. The proposed approach demonstrates that the optimal body bias reduces considerable amount of the leakage power in the nanoscale CMOS integrated circuits. In this approach, the temperature and supply voltage variations are compensated by the proposed feedback loop.Keywords-off-state, standby mode, sleep mode, leakage currents, sub-threshold leakage current, band-to-band tunneling (BTBT) leakage current I.978-1-4244-3353-7/09/$25.00 ©2009 IEEE

Accurate leakage current models for MOSFET nanoscale devices

“…Carriers move along the surface like the charge transport, and the subthreshold conductions are limited by the diffusion current. The weak inversion current equation is expressed in [10]. Figure 1 shows the main MOSFET transistor terms (Source, Gate, and Drain) and the locations of each leakage currents sources.…”

“…Leakage current, in general, flows from the gate to the channel through the forbidden energy gap at the S iO2 layer when the potential of the oxide is lower than the barrier height (φ ox ). The calculation of the gate leakage is started by assuming that the gate voltage is equal to zero and based on the analytical model presented in [10]. The Gate to the inverted channel (I GC ) modeling contains two types of electrons tunneling mechanisms Fowler-Nordheim (FN) tunneling and direct tunneling.…”

Gate leakage current accurate models for nanoscale MOSFET transistors

“…The gate tunneling is one of the main leakage currents that has five components: the parasitic gate leakage from gate to SID overlap region (1go) and which creates two currents: (1gso) and (1gdo), the gate to the inverted channel leakage (1gc) which has two parts (1gcs) and(1gcd), and the gate to substrate leakage current (1gb ), [3]. The effect of gate voltage on gate overlapping leakage was ignored because the charge-image effect in reducing barrier height between SiO, insulator and Si which affected by the gate voltage.…”

“…Various literatures studied the Gate leakage current effect for Nanoscale technology [1][2][3][4][5]. The requirement of minimizing the Gate leakage is significantly increasing on lower scaling devices e. g. 22nm, making it the main motivation ..…”

Accurate subthreshold leakage model for nanoscale MOSFET transistor

“…These unwanted current components are tunneled due to reverse biasing and oxide thickness reduction between the gate and inversion channel at MOS transistor. Thus increases the power dissipation and propagation delay for the devices that fabricated using MOSFET transistors as in complementary metal oxide semiconductor (CMOS) inverter [1][2][3].…”