New driver/receiver CMOS circuits design, for lowpower VLSI applications, are proposed. They are based on the low swing technique. A significant reduction in power dissipation is achieved. due to the reduced swing voltage on the interconnection loads. Comparisons of the delay time of the proposed circuits with the conventional CMOS driver/receiver are presented. For different values of supply voltage, using 0.5pm process technology, SPICE measurements show up to 27% improvement in the total drivedreceiver power-delay product. Finally, circuits as repeaters are proposed for long interconnections.
SUMMARYThe influence of multi-threshold voltage technique on reducing the leakage power in CMOS circuits at transistor level based on Nanoscale SPICE parameters is investigated in this paper. Based on Artificial Intelligence search algorithms, three new algorithms are proposed to determine the exact threshold voltage for each transistor in order to minimize the leakage current at lowest value. These algorithms are: Slack Time Search Algorithm (STS), Leakage Power Search Algorithm (LPS), Leakage and Slack Time Search Algorithm (LSS). As a result, 70% of sub-threshold leakage current is reduced without degrading the performance. Based on 22 nm predictive SPICE parameters proposed by BSIM4, simulation results verified the validity of the proposed algorithms.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.