Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

Jeon, HeungJun; Kim, Yong-Bin; Choi, Minsu

doi:10.1109/tim.2010.2044710

Cited by 65 publications

(6 citation statements)

References 13 publications

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“…Figure 1 [18] shows the reduction of the subthreshold leakage current due to the increase in the barrier height and the reduction in V DS (= V DD -V m ) after stacking of two cutoff nMOS transistors in comparison with a single cutoff nMOS transistor. When both nMOS transistors, Q 1 and Q 2 are turned off due to the application of V GS < V TH , then the intermediate node voltage, V m has a positive value due to the existence of a small drain current.…”

Section: Methodology Adoptedmentioning

confidence: 99%

An Improved SOI CMOS Technology Based Circuit Technique for Effective Reduction of Standby Subthreshold Leakage

Kumar¹,

Hussain²,

Paul³

2013

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Silicon-on-insulator (SOI) CMOS technology is a very attractive option for implementing digital integrated circuits for low power applications. This paper presents migration of standby subthreshold leakage control technique from a bulk CMOS to SOI CMOS technology. An improved SOI CMOS technology based circuit technique for effective reduction of standby subthreshold leakage power dissipation is proposed in this paper. The proposed technique is validated through design and simulation of a one-bit full adder circuit at a temperature of 27˚C, supply voltage, V DD of 0.90 V in 120 nm SOI CMOS technology. Existing standby subthreshold leakage control techniques in CMOS bulk technology are compared with the proposed technique in SOI CMOS technology. Both the proposed and existing techniques are also implemented in SOI CMOS technology and compared. Reduction in standby subthreshold leakage power dissipation by reduction factors of 54x and 45x foraone-bit full adder circuit was achieved using our proposed SOI CMOS technology based circuit technique in comparison with existing techniques such as MTCMOS technique and SCCMOS technique respectively in CMOS bulk technology. Dynamic power dissipation was also reduced significantly by using this proposed SOI CMOS technology based circuit technique. Standby subthreshold leakage power dissipation and dynamic power dissipation were also reduced significantly using the proposed circuit technique in comparison with other existing techniques, when all circuit techniques were implemented in SOI CMOS technology. All simulations were performed using Microwindver 3.1 EDA tool.

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Section: Methodology Adoptedmentioning

confidence: 99%

An Improved SOI CMOS Technology Based Circuit Technique for Effective Reduction of Standby Subthreshold Leakage

Kumar¹,

Hussain²,

Paul³

2013

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“…Therefore, a significant amount of power will be spent on retaining data in idling memory units . With ever‐increasing number of transistors on a chip, such standby power consumption increases dramatically and is now limiting further device miniaturization . For this reason, non‐volatile memory capability is one of the desirable core attributes for all emerging RAM technologies such as ferroelectric random access memory (FeRAM), phase change memory (PCM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM) .…”

Section: Electrically Driven Magnetization Switching (Edms)mentioning

confidence: 99%

“…[ 5 ] With ever-increasing number of transistors on a chip, such standby power consumption increases dramatically and is now limiting further device miniaturization. [ 202 ] For this reason, non-volatile memory capability is one of the desirable core attributes for all emerging RAM technologies such as ferroelectric random access memory (FeRAM), phase change memory (PCM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM). [ 203 ] Among them, MRAM probably enjoys the most immediate relevance to applications in personal computers, [ 203 ] with commercial products launched by different companies (e.g., Everspin technologies, Inc. and Grandis, Inc.).…”

Section: Reviewmentioning

confidence: 99%

Multiferroic Heterostructures Integrating Ferroelectric and Magnetic Materials

2015

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Multiferroic heterostructures can be synthesized by integrating monolithic ferroelectric and magnetic materials, with interfacial coupling between electric polarization and magnetization, through the exchange of elastic, electric, and magnetic energy. Although the nature of the interfaces remains to be unraveled, such cross coupling can be utilized to manipulate the magnetization (or polarization) with an electric (or magnetic) field, known as a converse (or direct) magnetoelectric effect. It can be exploited to significantly improve the performance of or/and add new functionalities to many existing or emerging devices such as memory devices, tunable microwave devices, sensors, etc. The exciting technological potential, along with the rich physical phenomena at the interface, has sparked intensive research on multiferroic heterostructures for more than a decade. Here, we summarize the most recent progresses in the fundamental principles and potential applications of the interface-based magnetoelectric effect in multiferroic heterostructures, and present our perspectives on some key issues that require further study in order to realize their practical device applications.

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“…Circuit optimization provides Low power and high performance. Circuit optimization can be obtained through simultaneous gate sizing and threshold voltage (Vt) assignment [13]- [14]. Sleep transistor method provides good reduction in leakage power, but it is a state destructive technique.…”

Section: Leakage Current Reductionmentioning

confidence: 99%

Leakage Power Reduction in CMOS VLSI Circuits

Saini¹,

Mehra²

2012

IJCA

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Leakage power has become a serious concern in nanometer CMOS technologies. In the past, the dynamic power has dominated the total power dissipation of CMOS devices. However, with the continuous trend of technology scaling, leakage power is becoming a main contributor to power consumption. In the past many methods had been proposed for leakage power reduction like forced stack, sleepy stack, sleepy keeper, dual sleep approach etc. using techniques like transistor sizing, multi-Vth, dual-Vth, stacking transistors etc. In this paper, new methods have been proposed for the leakage power reduction in 90nm technology. The proposed methods will be compared with the previous existing leakage reduction techniques. The result is simulated using Microwind 3.1 in 90nm CMOS technology at room temperature.

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Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

Cited by 65 publications

References 13 publications

An Improved SOI CMOS Technology Based Circuit Technique for Effective Reduction of Standby Subthreshold Leakage

An Improved SOI CMOS Technology Based Circuit Technique for Effective Reduction of Standby Subthreshold Leakage

Multiferroic Heterostructures Integrating Ferroelectric and Magnetic Materials

Leakage Power Reduction in CMOS VLSI Circuits

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