Low-power high-speed low-offset fully dynamic CMOS latched comparator

Jeon, HeungJun

doi:10.17760/d20000933

Cited by 7 publications

(5 citation statements)

References 29 publications

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“…The average power consumption, time delay, offset voltage and power delay product results are found very promising and shown the proposed comparator's supremacy while compared with other recent works, designed using the same technology. Vdd (V) Power Consumption (uW) [11] [12]…”

Section: Discussionmentioning

confidence: 99%

“…The dynamic comparator presented in fig. 1 is designed by HeungJun Jeon et al [11]. This comparator operates in two clock cycles.…”

Section: Dynamic Latch Comparatorsmentioning

confidence: 99%

“…Moreover, the power consumption for all of the comparators increased with the progression of the supply voltage which is quite obvious. Delay (ps) [11] [ The detailed performance comparisons of our proposed comparator with other similar works have been presented in Table I. The supply voltage, differential input voltage and operating frequency are held same at 0.8 V, 5 mV and 5 GHz, respectively for all of the comparators to show the proper contrasts.…”

Section: Proposed Dynamic Latch Comparatormentioning

confidence: 99%

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Analysis and Design of a 32nm FinFET Dynamic Latch Comparator

Hossain

Biswas

2019

2019 5th International Conference on Advances in Electrical Engineering (ICAEE)

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Comparators have multifarious applications in various fields, especially used in analog to digital converters. Over the years, we have seen many different designs of single stage, dynamic latch type and double tail type comparators based on CMOS technology, and all of them had to make the tradeoff between power consumption and delay time. Meanwhile, to mitigate the short channel effects of conventional CMOS based design, FinFET has emerged as the most promising alternative by owning the tremendous gate control feature over the channel region. In this paper, we have analyzed the performance of some recent dynamic latch type comparators and proposed a new structure of dynamic latch comparator; moreover, 32nm FinFET technology has been considered as the common platform for all of the comparators circuit design. The proposed comparator has shown impressive performance in case of power consumption, time delay, power delay product and offset voltage while compared with the other recent comparators through simulations with LTspice.

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Section: Discussionmentioning

confidence: 99%

“…The dynamic comparator presented in fig. 1 is designed by HeungJun Jeon et al [11]. This comparator operates in two clock cycles.…”

Section: Dynamic Latch Comparatorsmentioning

confidence: 99%

Section: Proposed Dynamic Latch Comparatormentioning

confidence: 99%

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Analysis and Design of a 32nm FinFET Dynamic Latch Comparator

Hossain

Biswas

2019

2019 5th International Conference on Advances in Electrical Engineering (ICAEE)

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“…A high-speed fully-dynamic double-tail latch (DTL) composed of a pre-amplifier and an output latch has been chosen as comparator [23], [24], and is depicted in Fig. 5.…”

Section: Dynamic Comparatormentioning

confidence: 99%

“…. With respect to the scheme in [24], we added two additional programmable capacitors and to the input and the output of the inverter to filter the comparator noise [25]. The capacitor is dimensioned to make the noise of the inverter negligible.…”

Section: Dynamic Comparatormentioning

confidence: 99%

A Reconfigurable 5-to-14 bit SAR ADC for Battery-Powered Medical Instrumentation

Fateh

Schonle

Bettini

et al. 2015

IEEE Trans. Circuits Syst. I

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In battery-powered medical instrumentation, the resolution and signal bandwidth of analog-to-digital converters (ADCs) have to be adapted to the needs of the application to avoid power wastage. This paper presents a reconfigurable successive approximation register (SAR) ADC implemented in 130 nm CMOS that resolves 5-14 bit with a maximum achievable effective number of bits (ENOB) of 13.5 using non-subtractive dither. In the proposed ADC design, the power consumption can be traded for accuracy to improve the energy efficiency and extend its application range, while reducing system integration complexity. A figure-of-merit (FoM) of 59 fJ/conversion is achieved at 1.2 V supply and the converter occupies an area of 0.42 . Measurement results of the ADC integrated in a multi-channel analog front-end (AFE) circuit show the suitability of the ADC for portable medical monitoring devices.

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