Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Abstract

Abstract-This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this paper. Our optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. We present three control policies: 1) progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2) progressive-on-stateaging (POSA), which estimates aging by tracking active/sleep modes, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; and 3) progressive-real-timeaging-assisted (PRTA), which acquires real-time information and initiates optimized control actions. Various flavors of these control policies for systems with dynamic voltage and frequency scaling (DVFS) are also analyzed. Simulation results on benchmark circuits, using aging models validated by 45 nm measurements, demonstrate the effectiveness and practicality of our approach in significantly improving LCPE and/or lifetime compared to traditional one-time worst-case guardbanding. We also derive system design guidelines to maximize self-tuning benefits.Index Terms-Adaptive supply voltage and clock frequency, circuit aging, energy-efficiency, lifetime reliability.

ReSCALE: Recalibrating sensor circuits for aging and lifetime estimation under BTI

“…3. There are several existing schemes that can be used to measure the runtime delay of a circuit such as the Path-RO [13], delay shift circuits [12], [14], or the techniques described in [5]. These schemes require onchip test patterns (to sensitize critical paths), also shown in Fig.…”

“…As a result, chip design teams often treat SP-based methods with skepticism. Post-silicon techniques, on the other hand, rely on data from surrogate aging sensors [2]- [4], such as ring oscillators, to apply just enough adaptive compensation to mitigate the effect of aging [5], [6]. To a limited extent, they may successfully capture the environment faced by the circuit, e.g., if they are placed close to the circuit and have a similar connection to the power grid, they can capture the thermal and supply voltage environment.…”

“…Such pessimistic delays, typically used to define a presilicon aging margin, may result in high power/area overheads during optimization [1], [5].…”

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

“…Static variations, primarily process variations [1], do not change over time and typically affect the worst-case path of each die. Dynamic variations, such as changes in temperature [2][3][4][5], voltage [2][3][4][5], and aging [6], change over time and require in-situ methods to combat degradation of performance.…”

“…Some sources of variation such as supply voltage fluctuations may vary frequently (on the order of a few clock cycles) [9] while others such as aging vary over large periods of time (such as several years) [6]. Because of their dynamic and difficult to predict nature, it becomes much more difficult to design resilient systems to combat these variations.…”