Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

Abstract

While Moore's law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit J. Low Power Electron. Appl. 2011, 1 335 approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well.

Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters

“…We assume that every processor has one delay fault tester that can detect failures in the read/write operation during boot or by periodically testing. Several delay fault detectors are proposed in the literature [12], [13], such as functional testers, architectural retiming, tunable replica circuits, Razor flipflops, and software level error detection techniques [13]. If the tester does not find any timing error, it sends a no-error signal to the reconfigurable pipeline.…”

Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling

“…Therefore, a challenge of timing speculation based voltage overscaling lies in reducing overall timing penalty for error corrections. There have been several error correction methods [1], [2], [5], [6], [13], [14]. Among them, instruction replay [5] has the smallest design overhead.…”

“…Micro-rollback [13], [14] saves previous data of each pipeline stage to backup storage in each cycle. When the error signal reaches the last stage, the backup storage injects the last known correct data to each pipeline stage.…”

Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS

“…There are two main types of EDS architectures: a dynamic node [13][14][15] and a delayed shadow latch [7,8]. Of these architectures, the dynamic node can achieve a lower power and lower clock node capacitance.…”

“…By allowing for the detection and correction of timing errors, TED systems are able to reduce the safety margins required to ensure the correct timing under PVTA variations [6][7][8]. Furthermore, TED can be used to mitigate thermal and power supply variations across the chip in massively parallel systems and take into account the effects of ageing without extra effort.…”