Resonant-Clock Latch-Based Design

Abstract-Clock distribution networks consume a significant portion of total chip power in high-performance designs. Resonant clocks are one proposed method to lower this power in modern designs as well as a fewer required clock buffers. Recent resonant solutions are limited to optimal performance at one particular frequency which is problematic since dynamic frequency scaling is often used to lower overall system power. This paper introduces the first scheme to produce a clock distribution network with a tunable resonant frequency. Experimental results show the resonant frequency ranges from 1.2GHz to 2.6GHz while saving up to 41% of the power on the clock distribution network when compared to the non-resonant distribution.

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“…2 [12], [13]. Our designs are created using Sonnet EM Suite [14] and modeled in HSPICE like Figure 2(a).…”

Section: A Inductor Designmentioning

confidence: 99%

“…We use transistor sizes of 0.95µm for PMOS and 0.63µm for NMOS. This sizing ratio and circuit are influenced by AMD and Cyclos [12], [13]. Both transistors are sized as small as possible while maintaining full signal swing in transient analysis.…”

Section: B Lc Tank Designmentioning

confidence: 99%

Multi-frequency resonant clocks

LaCara

Lin

Guthaus

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…The design rule was 0. 18 . The power supply voltage was 1.8 V. and were 200 and 1000 pF, respectively.…”

Section: A Circuit Structurementioning

confidence: 99%

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

Nakata

Honda

Makino

et al. 2012

IEEE Trans. Circuits Syst. I

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The stability of a stepwise waveform of an adiabatic charge recycling circuit with tank capacitors is investigated. We propose a new tank capacitor circuit with two-string capacitor arrays. We experimentally confirmed the stability of the five-step waveform from the tank capacitors. The voltage changes of tank capacitors in the experiment are consistent with the simulation. The power consumption is reduced to one-fifth due to the five-step waveform. We analyze the stability using matrix theory. The results prove that the step waveform is stable for any circuit topology. Moreover, we consider the effects of conductors fixed at a certain voltage and floating conductors and confirm the system is stable using matrix theory.

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“…Energy-recovering logic has demonstrated great potential when driving large capacitive loads and circuits utilizing this technique have been successfully implemented in the past [1], [5]. Energy-recovering designs can break the C · V DD energy limit of conventional static CMOS, by spreading out charge transfer more evenly over an entire switching period and thus making energy dissipation proportional to the operating frequency [3].…”

Section: Introductionmentioning

confidence: 99%

Evaluation of energy-recovering interconnects for low-power 3D stacked ICs

Asimakopoulos

Plas

Yakovlev

et al. 2009

2009 IEEE International Conference on 3D System Integration

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Abstract-Energy-recovering schemes have been proposed in the literature as an alternative approach to low-power design, while their performance has been demonstrated to be extremely promising when driving large capacitive loads, such as clock distribution networks [1]. This work investigates the potential of the energy-recovering methodology for improving the energy efficiency of through-silicon via (TSV) interconnects in 3D ICs.

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Resonant-Clock Latch-Based Design

Cited by 40 publications

References 13 publications

Multi-frequency resonant clocks

Multi-frequency resonant clocks

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology

Evaluation of energy-recovering interconnects for low-power 3D stacked ICs

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