Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor

Sathe, Visvesh; Arekapudi, S.; Ishii, Alexander T.; Ouyang, C.; Papaefthymiou, Marios C.; Naffziger, Samuel

doi:10.1109/jssc.2012.2218068

Cited by 51 publications

(42 citation statements)

References 11 publications

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“…With maintenance of low clock skew, the resonant global CDN efficiently reduced the clock distribution power. Sathe et al [15] implemented dual mode feature to minimize the area and average power dissipation for maximum constrained performance. The implementation of a core in conventional and resonant mode at frequencies higher than the natural frequency achieved the energy-efficient clocking.…”

Section: Related Workmentioning

confidence: 99%

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

2018

Teh. vjesn.

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High-clock skew variations and degradation of driving ability of buffers lead to an additional power dissipation in Clock Distribution Network (CDN) that increases the dimensionality of buffers and coordination among flip-flops. The manual threshold level to predict the Region of Interest (ROI) is not applicable in clustering process due to the complexities of excessive wire length and critical delay. This paper proposes the Distance and Load Weight Updated Clustering (DLWUC) to determine the suitable position of logical components. Initially, the DLWUC utilizes the Hybrid Weighted Distance (HWD) to estimate the distance and construct the distance matrix. The weight value extracted from the sorted distance matrix facilitates the projection of buffers. The updated weight value serves as the base for clustering with labeled outputs. The placement of buffer at the suitable place from load weight updated clustering provides the necessary trade-off between clock provision and load balance. The DLWUC discussed in this paper reduces the size of buffers, skew, power and latency compared to the existing topologies.

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Section: Related Workmentioning

confidence: 99%

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

2018

Teh. vjesn.

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“…2 [12], [13]. Our designs are created using Sonnet EM Suite [14] and modeled in HSPICE like Figure 2(a).…”

Section: A Inductor Designmentioning

confidence: 99%

“…We use transistor sizes of 0.95µm for PMOS and 0.63µm for NMOS. This sizing ratio and circuit are influenced by AMD and Cyclos [12], [13]. Both transistors are sized as small as possible while maintaining full signal swing in transient analysis.…”

Section: B Lc Tank Designmentioning

confidence: 99%

Multi-frequency resonant clocks

LaCara

Lin

Guthaus

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Clock distribution networks consume a significant portion of total chip power in high-performance designs. Resonant clocks are one proposed method to lower this power in modern designs as well as a fewer required clock buffers. Recent resonant solutions are limited to optimal performance at one particular frequency which is problematic since dynamic frequency scaling is often used to lower overall system power. This paper introduces the first scheme to produce a clock distribution network with a tunable resonant frequency. Experimental results show the resonant frequency ranges from 1.2GHz to 2.6GHz while saving up to 41% of the power on the clock distribution network when compared to the non-resonant distribution.

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“…Microprocessor performance is becoming power limited and the use of resonant clocking to reduce power consumption has seen increasing interest [1][2][3]. POWER8 TM core plus L2 clock power was reduced by 33%, compared to a non-resonant baseline design, when using resonant clocking [3].…”

Section: Introductionmentioning

confidence: 99%

Optimization and modeling of resonant clocking inductors for the POWER8<sup>TM</sup> microprocessor

Groves

Restle

Drake

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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A parameterized model for resonant clocking inductors embedded in a dense power grid was developed using extensive electromagnetic simulations. The resulting model was used to support resonant clock designs for the POWER8 TM microprocessor. The model enabled tuning of the inductance attached to each clock sector to optimize its resonant behavior, resulting in a 33% reduction in clock power. Simulations using the model showed excellent agreement with measurement for inductance, Q and global clock power. Inductor to inductor and inductor to flip-chip solder ball interaction was minimized by shielding provided by the dense power grid.

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Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor

Cited by 51 publications

References 11 publications

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

DLWUC: Distance and Load Weight Updated Clustering-Based Clock Distribution for SOC Architecture

Multi-frequency resonant clocks

Optimization and modeling of resonant clocking inductors for the POWER8<sup>TM</sup> microprocessor

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