MATIC: Learning around errors for efficient low-voltage neural network accelerators

Abstract

As a result of the increasing demand for deep neural network (DNN)-based services, efforts to develop dedicated hardware accelerators for DNNs are growing rapidly. However, while accelerators with high performance and efficiency on convolutional deep neural networks (Conv-DNNs) have been developed, less progress has been made with regards to fullyconnected DNNs (FC-DNNs). In this paper, we propose MATIC (Memory Adaptive Training with In-situ Canaries), a methodology that enables aggressive voltage scaling of accelerator weight memories to improve the energy-efficiency of DNN accelerators. To enable accurate operation with voltage overscaling, MATIC combines the characteristics of destructive SRAM reads with the error resilience of neural networks in a memory-adaptive training process. Furthermore, PVT-related voltage margins are eliminated using bit-cells from synaptic weights as in-situ canaries to track runtime environmental variation. Demonstrated on a low-power DNN accelerator that we fabricate in 65 nm CMOS, MATIC enables up to 60-80 mV of voltage overscaling (3.3× total energy reduction versus the nominal voltage), or 18.6× application error reduction.

On the Resilience of Deep Learning for Reduced-voltage FPGAs

“…The verification of the simulation-based works on the real fabric can be a crucial concern; also, the real hardware works are mostly performed on the customized ASICs, which of course, reproducing those results on the COTS systems is a crucial question. On the other hand, there are not thorough efforts on the resilience of the DNN training phase; recent works in part cover the study in this area [24], [25], [40]- [42]. For instance, [41], [42] have analyzed only the fully-connected model of DNNs, [24] carried out the analysis on a customized ASIC model of the DNN, and finally, [25] performed a simulationbased study.…”

“…On the other hand, there are not thorough efforts on the resilience of the DNN training phase; recent works in part cover the study in this area [24], [25], [40]- [42]. For instance, [41], [42] have analyzed only the fully-connected model of DNNs, [24] carried out the analysis on a customized ASIC model of the DNN, and finally, [25] performed a simulationbased study. Our paper extends the study on the resilience of the DNN training, especially by using the fault maps of lowvoltage SRAM-based on-chip memories of real FPGA fabrics.…”

Exploiting Errors for Efficiency

“…Once the network has been quantized and compressed, we can further leverage resource versus correctness tradeoffs by storing the weights in approximate SRAM [142], which occasionally produces read errors. Recent work [96] shows that correct retraining and fault detection mechanisms can mitigate the negative effects of SRAM read upsets on classification tasks.…”

Deep Learning for Edge Computing: Current Trends, Cross-Layer Optimizations, and Open Research Challenges

“…In memories, aggressive voltage scaling is one of the most prominent approaches which can lead to significant efficiency gains. Towards this, Kim et al [33] proposed MATIC, a memory-adaptive training approach that enables aggressive voltage scaling of ac- 1 Weight Stationary: maximize convolutional reuse and filter reuse, Output Stationary: maximize partial sum accumulation and input feature map reuse. Row Stationary: maximize all these parameters.…”