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Interconnect solutions for advanced technology nodes using PECVD techniques for low-k deposition require the use of porogen-based process with post deposition UV cure. By using two different UV cure lamps (A, B) in combination with different porogen loads, three different micro-porous low-k films are developed: Aurora ELK HM (k~2.5; porosity (P) ~25%), Aurora ELK A (k~2.3; P~34%) and Aurora ELK B (k~2.2; P~37%). Integrating these materials is complex and challenging. We discuss key factors that are instrumental to the extension of a metal hard mask (MHM)-based integration scheme to these 3 low-k films. Our findings: (I) for sub-100nm dimensions, patterning and low-k interactions affect the dynamic of organic residue formation and thereby impact electrical yield; (II) choosing the right ash, etch and clean sequence is mandatory to control plasma damage, profile, residues and corrosion on top of the MHM; (III) Cu reduction plasmas must be adjusted when porosity is increased to mitigate field damage.

We report on a major advancement in full-field EUV Lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186µm 2 6T-SRAMs, with W-filled contacts. Alignment to other 193nm immersion litho levels shows very good overlay values ≤20nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3σ≤7nm after double-dipole 193nm immersion litho (NA=0.85) and 3σ≤9nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM V DD scalability down to 0.6V (SNM>0.1V DD ) and healthy electrical characteristics (V T , σ(∆V T ), I-V) for the cell transistors are obtained.

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With continuously shrinking design rules and corresponding low-k1 lithography, defectivity and yield are increasingly dominated by systematic patterning defects. The size of these yield-limiting defects is shrinking along with feature size, making their detection and verification more difficult. We discuss a novel, holistic approach to pattern defect detection and control, which integrates full chip layout analysis and hybrid wafer metrology data to predict wafer locations with highest probability for defect occurrence. We assess the various components of this flow by an experimental study on a 10 nm BEOL process at IMEC, using state-of-the-art negative tone development (NTD) and triple Litho-Etch patterning process. Downloaded From: http://proceedings.spiedigitallibrary.org/ on 05/19/2015 Terms of Use: http://spiedl.org/terms Proc. of SPIE Vol. 9424 94241B-2 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 05/19/2015 Terms of Use: http://spiedl.org/terms Proc. of SPIE Vol. 9424 94241B-8 Downloaded From: http://proceedings.spiedigitallibrary.org/ on 05/19/2015 Terms of Use: http://spiedl.org/terms

We report high yield sub-0.1μm 2 SRAM cells using high-k/metal gate finfet devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal1. 0.099μm 2 finfet 6T-SRAM cells show good yield. And smaller cells (0.089μm 2 ) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.

A strong demand exists for techniques that extend application of ArF immersion lithography. Besides techniques such as litho-friendly design, dual exposure/patterning schemes, customized illumination, alternative processing schemes are also viable candidates. One of the most promising alternative flows uses image reversal by means of a negative tone development (NTD) step with a Fujifilm solvent-based developer. Traditionally, contact and trench printing uses a dark-field mask in combination with positive tone resist and positive tone development. With NTD, the same features are printed in positive resist using light-field masks, and consequently with better image contrast. We present an overview of NTD applications, comparing the NTD performance to that of the traditional development. Experimental work is performed at a 1.35 numerical aperture, targeting the contact/metal layers of the 32-and 22-nm nodes. For contact printing, we consider both single-and dual-exposure schemes for regular arrays and 2-D patterns. For trench printing, we study 1-D, line end, and 2-D patterns. We also assess the etch capability and critical dimension uniformity performance of the NTD process. We proves the added value of NTD. It enables us to achieve a broader pitch range and/or smaller litho targets, which makes NTD attractive for the most advanced lithography applications, including double patterning. C 2010 Society of Photo-Optical Instrumentation Engineers.