2015
DOI: 10.1117/12.2087178
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A new paradigm for in-line detection and control of patterning defects

Abstract: With continuously shrinking design rules and corresponding low-k1 lithography, defectivity and yield are increasingly dominated by systematic patterning defects. The size of these yield-limiting defects is shrinking along with feature size, making their detection and verification more difficult. We discuss a novel, holistic approach to pattern defect detection and control, which integrates full chip layout analysis and hybrid wafer metrology data to predict wafer locations with highest probability for defect o… Show more

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Cited by 6 publications
(7 citation statements)
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“…The topography being a cause of focus intrafield excursions, this method allows the definition of care areas where focus margin will be reduced and defectivity may occur at a higher rate. The use of this data as an input for PWO [9,10] will allow an improved defect prediction. The care areas were also used as an input for a smart leveling methodology where the scanner will correct preferentially the critical areas of the chip.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…The topography being a cause of focus intrafield excursions, this method allows the definition of care areas where focus margin will be reduced and defectivity may occur at a higher rate. The use of this data as an input for PWO [9,10] will allow an improved defect prediction. The care areas were also used as an input for a smart leveling methodology where the scanner will correct preferentially the critical areas of the chip.…”
Section: Resultsmentioning
confidence: 99%
“…areas in which critical patterns in terms of imaging, determined by full chip LMC [9,10], and high local topography variation might be found, causing high probability of patterning failure. The capability of defining smart care areas is key for process improvement efficiency.…”
Section: -Modelling Topography With Gds Densitiesmentioning
confidence: 99%
“…The layout dependent local topography investigation in this paper is also linked to focus induced defectivity. The defect detection and control of this is covered in the paper and talk: A new paradigm for inline detection and control of patterning defects [8].…”
Section: Resultsmentioning
confidence: 99%
“…Nowadays, the designed feature size of IC is below 10 nm, and the number of transistors of an IC is as high as tens of billions [1,2]. With the demand for high integration and better performance, the physical design of IC continues to shrink, and the lithographic printability has become one of the critical issues in IC design and manufacturing [3,4]. Affected by the layout design and lithography process, the lithography results of some patterns in the layout are quite different from the target patterns, resulting in short-circuit or open-circuit problems.…”
Section: Introductionmentioning
confidence: 99%