Full-field EUV and immersion lithography integration in 0.186&amp;#x03BC;m&lt;sup&gt;2&lt;/sup&gt; FinFET 6T-SRAM cell

Veloso, A.; Demuynck, S.; Ercken, Monique; Goethals, Anne-Marie; Demand, M.; Marneffe, J.-F. de; Altamirano, E.; Keersgieter, A. De; Delvaux, Christie; Backer, J. De; Brus, S.; Hermans, Jan; Baudemprez, Bart; Roey, Frieda Van; Lorusso, Gian; Baerts, C.; Goossens, D.; Vrancken, C.; Mertens, S.; Versluijs, Janko; Truffert, Vincent; Huffman, C.; Laidler, David; Heylen, N.; Ong, Patrick; Parvais, B.; Rakowski, Michal; Verhaegen, Staf; Hikavyy, Andriy; Meiling, H.; Hultermans, Bas; Romijn, L.; Pigneret, C.; Lok, Sjoerd; Dijk, Andre van; Shah, Kavita; Noori, Atif; Gelatos, J.; Arghavani, Reza; Schreutelkamp, R.; Boelen, Pieter; Richard, Olivier; Bender, Hugo; Witters, L.; Collaert, N.; Rooyackers, R.; Absil, P.; Lauwers, A.; Jurczak, M.; Hoffmann, T.; Vanhaelemeersch, Serge; Cartuyvels, R.; Ronse, Kurt G.; Biesemans, S.

doi:10.1109/iedm.2008.4796834

Cited by 15 publications

(13 citation statements)

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“…There are a few basic reasons for that. The prototypes operational in the field have been able to demonstrate the feasibility of 32-and 22-nm node devices, [1][2][3][4][5][6] and preproduction tools are expected to be delivered by 2010. Optics contamination has been proven to be under control, and EUV-specific effects such as shadowing and flare, have been demonstrated to be quite predictable, hence, correctable.…”

Section: Introductionmentioning

confidence: 99%

Design correction in extreme ultraviolet lithography

Fenger

Lorusso

Hendrickx

et al. 2010

J. Micro/Nanolith. MEMS MOEMS

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Extreme ultraviolet (EUV) lithography is currently the most promising technology for advanced manufacturing nodes. This study aims to assess in detail the quality of a full chip optical correction for a EUV design, as well to discuss the available approaches to compensate for EUV-specific effects. Extensive data sets have been collected on the ASML EUV Alpha-Demo Tool using the latest Interuniversity Microelectronics Center baseline resist Shin-Etsu SEVR59. In total ∼1300 critical dimension (CD) measurements at wafer level and 700 at mask level were used as input for model calibration and validation. The smallest feature size in the data set was 32 nm. Both one-dimensional and twodimensional structures through CD and pitch were measured. The reticle used in this calibration exercise allowed one to modulate flare by varying tiling densities. The shadowing effect was modeled by means of a single bias correction throughout the design. Horizontal and vertical features of different types through pitch and CD were used to calibrate the shadowing correction. The model calibration yielded an root-mean square of ∼1 nm, which was observed to improve by including reticle CD data. An EUV mask fully corrected for optical proximity correction, flare and shadowing was fabricated and qualified, demonstrating the effectiveness of the implemented corrections. C 2010 Society of Photo-Optical Instrumentation Engineers.

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Section: Introductionmentioning

confidence: 99%

Design correction in extreme ultraviolet lithography

Fenger

Lorusso

Hendrickx

et al. 2010

J. Micro/Nanolith. MEMS MOEMS

View full text Add to dashboard Cite

show abstract

“…There are a few basic reasons for that. The prototypes operational in the field have been able to demonstrate the feasibility of 32nm and 22nm node devices [1][2][3][4][5][6], and pre-production tools are expected to be delivered by 2010. Optics contamination has been proven to be under control and EUV-specific effect such as shadowing and flare have been demonstrated to be quite predictable, hence correctable [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Full chip correction of EUV design

et al. 2010

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Extreme Ultraviolet Lithography (EUVL) is currently the most promising technology for advanced manufacturing nodes: it recently demonstrated the feasibility of 32nm and 22nm node devices, and pre-production tools are expected to be delivered by 2010. Generally speaking, EUVL is less in need of Optical Proximity Correction (OPC) as compared to 193nm lithography, and the device feasibility studies were indeed carried out with limited or no correction. However, a rigorous optical correction strategy and an appropriate Electronic Design Automation (EDA) infrastructure is critical to face the challenges of the 22nm node and beyond, and EUV-specific effects such as flare and shadowing have to be fully integrated in the correction flow and properly tested. This study aims to assess in detail the quality of a full chip optical correction for a EUV design, as well to discuss the available approaches to compensate for EUV-specific effects. Extensive data sets have been collected on the ASML EUV Alpha-Demo Tool (ADT) using the latest IMEC baseline resist Shin-Etsu SEVR59. In total about 1300 CD measurements at wafer level and 700 at mask level were used as input for model calibration and validation. The smallest feature size in the data set was 32nm. Both one-dimensional and twodimensional structures through CD and pitch were measured. The mask used in this calibration exercise allowed the authors to modulate flare by varying tiling densities within the range expected in the final design. The OPC model was fitted and validated against the CD data collected on the EUV ADT. The shadowing effect was modeled by means of a single bias correction throughout the design. Horizontal and vertical features of different type through pitch and CD were used to calibrate the shadowing correction, and the extent of the validity of the single bias approach is discussed. In addition, the quality of the generated full-chip flare maps has been tested against experimental results, and the model has been validated in the full flare range available within the mask. The model calibration yielded an RMS of about 1nm, and a EUV mask fully corrected for OPC, flare and shadowing was finally fabricated and qualified.

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“…Recent demonstrations using an alpha demo tool with full-field exposure at the 32-nm and 45-nm nodes for logic devices have shown EUVL to be suitable for HVM. 1,2 Our approach focuses on development in four key areas of lithography performance (exposure tool, resist material, mask fabrication technology, and mask data preparation technology) with the goal of getting EUVL ready for the HVM of devices with a half pitch (hp) of 40 nm (22-nm logic node). The EUV1 exposure tool has high-quality projection optics that provide an aberration as low as 0.6 nm rms and a flare as low as 10%.…”

Section: Introductionmentioning

confidence: 99%

“…The EUV1 exposure tool has high-quality projection optics that provide an aberration as low as 0.6 nm rms and a flare as low as 10%. 3 Regarding the resist, Selete standard resist 3 (SSR3) provides a high resolution of 26 nm and a high sensitivity of 10 mJ/cm 2 4 , 5 The mask structure was optimized to keep the image contrast high and mitigate mask shadowing, which arises from the use of a reflective mask and oblique illumination, by reducing the thickness of the absorber down to 51 nm. 6,7 A thinner absorber also provides a higher resolution and more accurate critical dimension (CD) control because it allows a thinner resist to be used for electron beam exposure.…”

Section: Introductionmentioning

confidence: 99%

Process liability evaluation for EUVL

Aoyama¹,

Tawarayama²,

Tanaka³

et al. 2009

Alternative Lithographic Technologies

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This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in these areas. The overall lithography performance was determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus, the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We found the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.

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Full-field EUV and immersion lithography integration in 0.186μm<sup>2</sup> FinFET 6T-SRAM cell

Cited by 15 publications

References 0 publications

Design correction in extreme ultraviolet lithography

Design correction in extreme ultraviolet lithography

Full chip correction of EUV design

Process liability evaluation for EUVL

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