In this work, Ru wires patterning by direct etch are evaluated for a potential 5 nm technology node. The characteristics of Ru etching by varying the bias voltage, total flow rate and Cl2/(O2+Cl2) gas flow ratio are studied in an inductively couple plasma etching chamber. Ru sidewalls profile with a tapering angle of 90° and Ru to SiO2 hard mask etch selectivity of 6 are achieved. The authors show the feasibility of patterning lines with an aspect ratio up to 3.5 and lines with a critical dimension down to 10.5 nm (with a 3σ line width roughness of 4.2 nm), which paves the way to further scaling of this approach. Finally, the authors present a study on Ru line roughness after patterning on 300 mm wafers. Here, they compare line roughness results of wafers where Ru is deposited with different deposition techniques, such as atomic layer deposition and plasma vapor deposition, and it is annealed after deposition at various temperatures.

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We demonstrate electrically functional 0.099μm 2 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) highk/metal gate FinFETs with L g~4 0nm, 12-17nm wide Fins, and cell β ratio~1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, ≥30nm-wide contacts. SRAM cell with SNM>10%V DD down to 0.4V, and healthy electrical characteristics for the cell transistors [SS~80mV/dec, DIBL~50-80mV/V, and V Tlin ≤0.2V (PMOS), V Tlin~0 .36V (NMOS)] are reported.

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The semiconductor industry has followed Moore's law for many decades and is currently preparing for high-volume manufacturing of the 7 nm technology node. To further scale down to the 5 nm technology node and below, research centers are constantly testing novel patterning and integration approaches. To enable a number of these new integration approaches, there is a growing need for a well-understood and well-controlled tone reversal technology. Tone reversal consists in inverting the tonality of all structures present on a wafer, e.g., turning a hole pattern into a pillar pattern. Examples of applications that advantageously integrate such tone reversal technology are multiple litho-etch block patterning, the fully self-aligned block concept, and the direct metal etch approach. A critical step in the tone reversal process is to achieve a good wafer planarization, i.e., limited wafer topography. This can be done by chemical mechanical polishing after filling the patterned features that need to be tone inverted. However, a more promising approach is to reduce the topography by using a planarizing spin-coating process to fill the patterns. Material vendors and research groups have done tremendous efforts to understand and improve the quality (uniformity, planarity, etch resistance, etc.) of spin-coating processes. When a spin-coating process is used to fill a given patterned structure, it is known that the degree of planarization is impacted by a set of parameters such as pattern width and density. However, it is not clear yet what the exact functional dependence is. In this work, the authors first present an experimental study of the planarization behavior of spin-coated materials as a function of pattern width, depth, and density. The authors observed a strong dependency of the width and the density of the patterns on the wafer topography post spin-coating, while the depth, within the boundaries of this study, showed no significant impact. The most striking result was the observation of the linear relationship between the pattern density difference between two areas and the relative height difference of those areas after spin-coating. Second, based on these experimental observations, the authors present a model that predicts the remaining wafer topography post spin-coating. The model calculates the topography for a given set of structures, using only one parameter as input. This parameter is a fixed number for a specific spin-coating process and is called the planarization length λ. The authors demonstrate that this model is capable of reproducing and predicting the experimentally measured height profiles on complex patterned structures for different spin-coating processes. These calculations can be done with commercially available electronic design automation software. Therefore, this model can become a powerful tool in mask design, both for applications based on tone reversal, and, in general, for patterning processes that make use of spin-coated materials.

Ruthenium and molybdenum are candidate materials to replace Cu as the back-end-of-line interconnect metal for the tightest pitch features for future technology nodes. Due to their better figure of merit ρ0 × λ (ρ0 bulk resistivity, λ electron mean free path), it is expected that the resistance of <10 nm wide Ru and Mo metal lines can be significantly reduced compared to Cu. An important advantage for Ru and Mo is that both materials, in contrast to Cu, can be patterned by means of so-called direct metal etch, through reactive ion etching or atomic layer etching and can potentially be implemented without barrier. An integration scheme with direct metal etch instead of damascene patterning could simplify the overall patterning flow and eventually opens the possibility for exploring new integration concepts and patterning approaches. However, the learning on direct metal etch of Ru and Mo in the literature is scarce, especially at the relevant dimensions of today's interconnects. In this work, we will focus on the major patterning challenges we have encountered during the development of direct metal etch processes for Ru at 18 nm pitch and Mo gratings at 32 nm pitch. We have observed that the direct metal etch of Ru at these small dimensions is impacted by the growth of an oxidized layer on the sidewalls of the hard mask, which originates from the sputtering of the hard mask in combination with the O2-based Ru etch chemistry. This results in a narrowing of the trenches to be patterned and can easily lead to an etch stop in the smallest features. We will discuss several mitigation mechanisms to remove this oxidized layer, as well as to avoid the formation of such a layer. For patterning Mo with a Cl2/O2-based chemistry, the major patterning challenges we encountered are the insufficient sidewall passivation and the oxidation of the patterned Mo lines. The sidewall passivation issue has been overcome with an in situ thin SiO2-like deposition after partial Mo etch, while a possible mitigation mechanism for the Mo oxidation could be the in situ encapsulation immediately after Mo patterning.

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