Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Gupta, Anshul; Pedreira, O. Varela; Arutchelvan, Goutham; Zahedmanesh, Houman; Devriendt, K.; Mertens, Hans; Tao, Zheng; Ritzenthaler, R.; Wang, Shouhua; Radisic, Dunja; Kenis, Karine; Teugels, Lieve; Sebai, Farid; Lorant, Christophe; Jourdan, N.; Chan, Boon Teik; Subramanian, Sharath; Schleicher, F.; Hopf, T.; Peter, A.; Rassoul, Nouredine; Debruyn, Haroen; Demonie, I.; Siew, Yong Kong; Chiarella, T.; Briggs, B.; Zhou, Xiuju; Rosseel, Erik; Keersgieter, A. De; Capogreco, E.; Litta, E. Dentoni; Boccardi, G.; Baudot, S.; Mannaert, G.; Sepúlveda, Mauricio; Mertens, S.; Kim, Min‐Soo; Dupuy, Emmanuel; Vandersmissen, K.; Paolillo, Sara; Yakimets, D.; Chehab, Bilal; Favia, P.; Drijbooms, Christel; Cousserier, Joris; Jaysankar, Manoj; Lazzarino, Frédéric; Morin, P.; Altamirano, E.; Mitard, J.; Wilson, Christopher J.; Holsteyns, Frank; Boemmels, Juergen; Demuynck, S.; Tőkei, Zsolt; Horiguchi, N.

doi:10.1109/ted.2020.3033510

Cited by 24 publications

(8 citation statements)

References 10 publications

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“…Ru and W are the two promising materials for BPR [ 8 , 9 , 10 ] for their high thermal budgets, relatively low resistance, and superior anti-electromigration properties. It has been reported that high-aspect-ratio (AR) Ru BPR demonstrates excellent resistivity reduction [ 8 ].…”

Section: Resultsmentioning

confidence: 99%

“…This effect increases the resistance–capacitance (RC) delay, current-resistance (IR) drop, and power consumption at M0 and M1, and thus deteriorates BEOL’s performance [ 3 ]. Many efforts have been devoted to improving the BEOL’s performance, from metallization to the structures’ perspective, respectively [ 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 ].…”

Section: Introductionmentioning

confidence: 99%

“…A typical attempt is to bury the power rails under shallow trench isolation (STI) and Si substrate, which is referred to as buried power rail (BPR) [ 8 ]. For example, a power distribution network (PDN) with BPR may achieve a 20% smaller area at the same technology node [ 10 ]. In the cases of front-side with buried power rails (FS-BPR), the power rails usually have larger aspect ratios (ARs) to lower their resistivity due to the limitation in the width direction.…”

Section: Introductionmentioning

confidence: 99%

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Mechanisms of Scaling Effect for Emerging Nanoscale Interconnect Materials

Zhao

et al. 2022

Nanomaterials

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The resistivity of Cu interconnects increases rapidly with continuously scaling down due to scatterings, causing a major challenge for future nodes in M0 and M1 layers. Here, A Boltzmann-transport-equation-based Monte Carlo simulator, including all the major scattering mechanisms of interconnects, is developed for the evaluation of electron transport behaviors. Good agreements between our simulation and the experimental results are achieved for Cu, Ru, Co, and W, from bulk down to 10 nm interconnects. The line resistance values of the four materials with the inclusion of liner and barrier thicknesses are calculated in the same footprint for a fair comparison. The impact of high aspect ratio on resistivity is analyzed for promising buried power rail materials, such as Ru and W. Our results show that grain boundary scattering plays the most important role in nano-scale interconnects, followed by surface roughness and plasma excimer scattering. Surface roughness scattering is the origin of the resistivity decrease for high-aspect-ratio conductive rails. In addition, the grain sizes for the technical nodes of different materials are extracted and the impact of grain size on resistivity is analyzed.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Mechanisms of Scaling Effect for Emerging Nanoscale Interconnect Materials

Zhao

et al. 2022

Nanomaterials

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“…In order to increase performance and minimize footprint, microelectronics have gone into the third dimension by connecting multiple die vertically with through-silicon vias (TSVs) or Cu-Cu connections [3]. At the die scale, transistor utilization can be increased by routing power through the backside for beyond 5 nm node CMOS [4] and is the enabling technology behind Intel's recently announced PowerVia [5]. These advancements present a unique challenge for failure analysis as both methods increase the amount of metallization between the active gate layer and the backside silicon surface, thus preventing optical access to the gate layers.…”

Section: Introductionmentioning

confidence: 99%

Vector Magnetic Current Imaging of an 8 nm Process Node Chip and 3D Current Distributions Using the Quantum Diamond Microscope

Oliver

Martynowych

Turne

et al. 2021

International Symposium for Testing and Failure Analysis

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The increasing trend for industry adoption of three-dimensional (3D) microelectronics packaging necessitates the development of new and innovative approaches to failure analysis. To that end, our team is developing a tool called the quantum diamond microscope (QDM) that leverages an ensemble of nitrogenvacancy (NV) centers in diamond for simultaneous wide fieldof- view, high spatial resolution, vector magnetic field imaging of microelectronics under ambient conditions [1,2]. Here, we present QDM measurements of two-dimensional (2D) current distributions in an 8 nm process node flip chip integrated circuit (IC) and 3D current distributions in a custom, multi-layer printed circuit board (PCB). Magnetic field emanations from the C4 bumps in the flip chip dominate the QDM measurements, but these prove to be useful for image registration and can be subtracted to resolve adjacent current traces on the micron scale in the die. Vias, an important component in 3D ICs, display only Bx and By magnetic fields due to their vertical orientation, which are challenging to detect with magnetometers that traditionally only measure the Bz component of the magnetic field (orthogonal to the IC surface). Using the multi-layer PCB, we demonstrate that the QDM's ability to simultaneously measure Bx, By, and Bz magnetic field components in 3D structures is advantageous for resolving magnetic fields from vias as current passes between layers. The height difference between two conducting layers is determined by the magnetic field images and agrees with the PCB design specifications. In our initial steps to provide further z depth information for current sources in complex 3D circuits using the QDM, we demonstrate that, due to the linear properties of Maxwell's equations, magnetic field images of individual layers can be subtracted from the magnetic field image of the total structure. This allows for isolation of signal from individual layers in the device that can be used to map embedded current paths via solution of the 2D magnetic inverse. Such an approach suggests an iterative analysis protocol that utilizes neural networks trained with images containing various classes of current sources, standoff distances, and noise integrated with prior information of ICs to subtract current sources layer by layer and provide z depth information. This initial study demonstrates the usefulness of the QDM for failure analysis and points to technical advances of this technique to come.

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“…An efficient alternative is provided by design-technology co-optimization (DTCO) [3]- [7]. This approach aims at answering process concerns with enhancements at higher design levels, as shown already through examples such as the Buried Power Rail (BPR) [8]- [10].…”

mentioning

confidence: 99%

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era

Sisto

Zografos

Chehab

et al. 2022

IEEE Trans. VLSI Syst.

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In this article, we provide a comprehensive evaluation of width modulation capabilities of both nanosheet (NS) and forksheet (FS) devices, going from device level to a block level implementation. The main innovation introduced by the FS consists of a dielectric wall added between the p-and nMOS transistors. Leveraging this feature, FS shows approximately the same current behavior as NS, considered a state-of-the-art reference, but reduced parasitic capacitance thanks to its fewer but wider stacked sheets. At block level, an area reduction up to 12% is observed with FS, alongside a 13% power reduction and 10% frequency increase. Following the device comparison, the potential of sheet width modulation as additional power, performance, and area (PPA) optimization technique during synthesis and place and route (PNR) is investigated. A description of the specific steps required to enable this knob in a conventional electronic design automation (EDA) framework is provided.As demonstrated by the obtained experimental results, the same frequency of the single-width implementation can be achieved using mixed libraries with lower power consumption (13% and 16% for NS and FS, respectively), leading to improved energy efficiency. Furthermore, it is shown how designs implemented using FS benefit more from this type of optimization than the ones using NS, with a 12%-15% energy reduction compared to the 8.5%-14% obtained with NS.

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Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Cited by 24 publications

References 10 publications

Mechanisms of Scaling Effect for Emerging Nanoscale Interconnect Materials

Mechanisms of Scaling Effect for Emerging Nanoscale Interconnect Materials

Vector Magnetic Current Imaging of an 8 nm Process Node Chip and 3D Current Distributions Using the Quantum Diamond Microscope

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era

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