High yield sub-0.1µm² 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

Abstract

We report high yield sub-0.1μm 2 SRAM cells using high-k/metal gate finfet devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal1. 0.099μm 2 finfet 6T-SRAM cells show good yield. And smaller cells (0.089μm 2 ) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.

Patterning challenges in setting up a 16nm node 6T-SRAM device using EUV lithography

“…The contact level uses rectangular local interconnects, besides the regular squared contact holes (CH). This rectangular interconnect design has already proven its benefit in electrical performance [5]. Care should be taken to get both, the rectangular and squared CHs, on the desired printed target.…”

“…The UL improves the adhesion on the used hardmask (HM) stack. Applied Materials' APF or amorphous carbon/SiOC HM is the standard for the front end layers and is a scaled down version of the HM stack used for the 22nm node patterning development [5]. The HM choice for the set-up of back-end patterning is still under discussion.…”

“…Currently, a scaling of the design towards 16nm node and characterization of the OPC needs is ongoing. The design that is targeted for in this work, with rectangular local interconnects on the contact layer, introduces more complexity in the metal1 layer, but shows, in the 22nm node SRAM cell, an improved electrical performance compared with the earlier used L-shaped local interconnects ( Figure 18) [5]. For the contact layer, two types of cells have been evaluated: a simple scaled version of our 22nm node design (90nm critical pitch) and an optimized cell where both types of CHs were separately sized (a kind of rule-based OPC).…”

“…The capability of using EUV lithography for the patterning of the contact and metal1 layer is already proven by imec's electrical functional 22nm node SRAM cell [5]. The contact plugs are transferred into an oxide layer using a multiple hardmask and filled with Tungsten [18].…”

“…Next to that, finFET devices are considered as the most promising option for allowing SRAM scaling to 22nm node and beyond, thanks to their improved short channel effects behavior [4][5]. In the past, imec already developed different generations of this cell, down to a 22nm node version, step by step, by introducing a litho-friendly design [1], increasing aggressiveness of resolution enhancement techniques [6][7][8] and layer specific lithographic process and related patterning development [2,5&9-10] (Figure 1).…”