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Uniaxial stressors have received much interest over the last few years as a method to enhance carrier mobility and, hence, drive current with minimal modification to the structure of the transistor. However, the shift in device design to complex structures with multiple crystallographic orientations like advanced bulk-FinFETs has significantly complicated the incorporation of mobility enhancing stressors. For the n-FinFET in particular, it turns out that the crystal quality and growth rate of Si:P and Si:C:P films can be strongly dependent upon the crystallographic orientation of the starting surface. Both for raised and recessed epi we find that formation of (111) facets and twin defects occurs already after a limited growth on the fin. Besides the growth on raised and recessed fins, we also discuss the resistivity increase in Si:C:P layers as a function of carbon content and demonstrate that laser annealed Si:P films with high phosphorus content (e.g. 4% or higher) can be considered as potential alternatives to Si:C:P with a lower resistivity for the same strain.

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Record-low contact resistivity (ρ c ) for n-Si, down to 1.5×10 -9 Ω•cm 2 , is achieved on Si:P epitaxial layer. We confirm that Ti silicidation reduces the ρ c for n-Si, while an additional Ge pre-amorphization implantation (PAI) before Ti silicidation further extends the ρ c reduction. In situ doped Si:P with P concentration of 2×10 21 cm -3 is used as the substrate, and dynamic surface anneal (DSA) boosts P activation. In addition, TiO x based metal-insulator-semiconductor (MIS) contact is also studied on Si:P but is found to suffer from low thermal stability.

With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures.

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