Au nanoparticles are efficient catalysts for the vapour-solid-liquid (VLS) growth of semiconductor nanowires, but Au poses fundamental reliability concerns for applications in Si semiconductor technology. In this work we show that the choice of catalysts for Si nanowire growth can be broadened when the need for catalytic precursor dissociation is eliminated through the use of plasma enhancement. However, in this regime the incubation time for the activation of VLS growth must be minimized to avoid burying the catalyst particles underneath an amorphous Si layer. We show that the combined use of plasma enhancement and the use of a catalyst such as In, already in a liquid form at the growth temperature, is a powerful method for obtaining Si nanowire growth with high yield. Si nanowires grown by this method are monocrystalline and generally oriented in the 111 direction.
Due to its high intrinsic mobility, germanium (Ge) is a promising candidate as a channel material (offering a mobility gain of approximately × 2 for electrons and × 4 for holes when compared to conventional Si channels). However, many issues still need to be addressed before Ge can be implemented in high-performance field-effect-transistor (FET) devices. One of the key issues is to provide a high-quality interfacial layer, which does not lead to substantial drive current degradation in both low equivalent oxide thickness and short channel regime. In recent years, a wide range of materials and processes have been investigated to obtain proper interfacial properties, including different methods for Ge surface passivation, various high-k dielectrics and metal gate materials and deposition methods, and different post-deposition annealing treatments. It is observed that each process step can significantly affect the overall metal-oxide-semiconductor (MOS)-FET device performance. In this review, we describe and compare combinations of the most commonly used Ge surface passivation methods (e.g. epi-Si passivation, surface oxidation and/or nitridation, and S-passivation) with various high-k dielectrics. In particular, plasma-based processes for surface passivation in combination with plasma-enhanced atomic layer deposition for high-k depositions are shown to result in high-quality MOS structures. To further improve properties, the gate stack can be annealed after deposition. The effects of annealing temperature and ambient on the electrical properties of the MOS structure are also discussed.
Vanadium dioxide (VO 2 ) has the interesting feature that it undergoes a reversible semiconductor-metal transition (SMT) when the temperature is varied near its transition temperature at 68°C. 1 The variation in optical constants makes VO 2 useful as a coating material for e.g. thermochromic windows, 2 while the associated change in resistivity could be interesting for applications in microelectronics, e.g. for resistive switches and memories. Due to aggressive scaling and increasing integration complexity, atomic layer deposition (ALD) is gaining importance for depositing oxides in microelectronics. However, attempts to deposit VO 2 by ALD result in most cases in the undesirable V 2 O 5 .In the present work, we demonstrate the growth of VO 2 by using Tetrakis[EthylMethylAmino]Vanadium and ozone in an ALD process at only 150°C. XPS reveals a 4+ oxidation state for the vanadium, related to VO 2 . Films deposited on SiO 2 are amorphous, but during a thermal treatment in inert gas at 450°C VO 2 (R) is formed as the first and only crystalline phase. The semiconductor-metal transition has been observed both with in-situ X-ray diffraction and resistivity measurements. Near a temperature of 67°C, the crystal structure changes from VO 2 (M1) below the transition temperature to VO 2 (R) above with a hysteresis of 12°C. Correlated to this phase change, the resistivity varies over more than 2 orders of magnitude. This work has been accepted for publication in Applied Physics Letters. The inset shows the in-situ XRD measurement from which the peak intensity was integrated.
679wileyonlinelibrary.com attractive for potential applications, such as nanoelectronic switches, [3][4][5] transistors, [ 6 ] optical devices, [ 7,8 ] and micromechanical devices. [ 9 ] VO 2 thin fi lms have been synthesized by a variety of deposition techniques, such as pulsed laser deposition (PLD), [10][11][12][13][14] molecular beam epitaxy (MBE), [ 15 ] reactive sputtering, [ 16,17 ] sol-gel processing, [ 18 ] chemical vapor deposition (CVD), [ 19 ] thermal oxidation, [ 20 ] and ion beam deposition. [ 21,22 ] Most of the studies report on VO 2 fi lms with thicknesses in the range of 40-200 nm. Sub-10 nm continuous fi lms of ≈2 nm thickness have been deposited both by PLD [ 23 ] and MBE [ 15 ] on monocrystalline TiO 2 and MITs with resistivity changes of ≈500 × and ≈25 × , respectively. However, the use of TiO 2 monocrystals as a substrate is unfavorable for practical nanoelectronic applications and PLD and MBE are not deposition techniques that are well suited for device manufacturing. By contrast, VO 2 fi lms deposited by techniques suitable for manufacturing, including atomic layer deposition (ALD), have typically been noncontinuous and have shown a strongly degraded MIT when the fi lm thicknesses were below 40-50 nm. [24][25][26] In recent years, ALD [ 27,28 ] has become the reference technique for the deposition of dielectric [ 29 ] and metallic [ 30 ] thin fi lms for nanoelectronic applications. [31][32][33] ALD is characterized by self-limiting surface reactions, which enables a precise control over fi lm thickness and stoichiometry. In addition, the high conformality allows deposition onto three-dimensional (3D) structures, as increasingly required for advanced nanoelectronic applications. However, the ALD growth of thin high quality VO 2 is not established yet. VO 2 ALD has been reported using vanadyl acetonate and O 2 [ 34 ] or VOCl 3 . [ 35 ] X-ray diffraction (XRD) indicated the presence of VO 2 and signs of MITs have been observed. Yet, these processes have not been able to achieve thin, continuous, and phase-pure fi lms. By contrast, the ALD from tetrakis(ethylmethylamino) vanadium (TEMAV) and O 3 has led to continuous smooth fi lms that show an MIT down to a thickness of ≈40 nm. [36][37][38][39] ALD VO 2 from TEMAV with H 2 O as oxygen source has been reported to lead to mixed valence VO x fi lms which can be converted to VO 2 by postannealing. [ 40 ] Nevertheless, no continuous ALD VO 2 fi lms featuring an MIT Nanoscale morphology of vanadium dioxide (VO 2 ) fi lms can be controlled to realize smooth ultrathin (<10 nm) crystalline fi lms or nanoparticles with atomic layer deposition, opening doors to practical VO 2 metal-insulator transition (MIT) nanoelectronics. The precursor combination, the valence of V, and the density for as-deposited VO 2 fi lms, as well as the postdeposition crystallization annealing conditions determine whether a continuous thin fi lm or nanoparticle morphology is obtained. It is demonstrated that the fi lms and particles possess both a structural and an electronic t...
Vanadium oxide (VO2) thin films were prepared by atomic layer deposition using TEMAV (tetrakis[ethylmethylamido]vanadium) precursor and ozone as the reactant gas. Study on the precursor as well as oxidizer doses and temperature dependence showed none of them exhibited the characteristics of ideal ALD. The VO2 phase formation pathways, its process window, and surface roughness are found to be sensitive to the anneal conditions applied and the substrate used. The VO2 morphology on Al2O3 was found to be island-like whereas on Si/SiO2 either a nano particle formation or a continuous film was obtained. GIXRD demonstrated the VO2 crystallization window to be very narrow on Al2O3 and thick SiO2 while a relatively broad window is obtained on 1 nm SiO2. A reversible change in sheet resistance was measured with more than three orders of magnitude for a 30 nm film.
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