Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

Mertens, Hans; Ritzenthaler, R.; Chasin, Adrian; Schram, T.; Kunnen, E.; Hikavyy, Andriy; Ragnarsson, Lars‐Åke; Dekkers, Harold; Hopf, T.; Wostyn, Kurt; Devriendt, K.; Chew, Soon Aik; Kim, M. S.; Kikuchi, Yoshihiro; Rosseel, Erik; Mannaert, G.; Kubicek, S.; Demuynck, S.; Dangol, A.; Bosman, N.; Geypen, J.; Carolan, P.; Bender, Hugo; Barla, K.; Horiguchi, N.; Mocuta, D.

doi:10.1109/iedm.2016.7838456

Cited by 110 publications

(41 citation statements)

References 6 publications

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“…x Þ is the cross-correlation power spectrum of M n 0 l 0 nl ½Dðs; xÞ and M n 0 g 0 ng ½Dðs 0 ; x 0 Þ; an explicit expression for S n 0 ;l 0 g 0 n;lg ðq s ; q 0 x Þ will be discussed below. Equation (14) has been written for a continuous q x , which implies a large normalization length along the x direction; Eq. 14also assumes that the length D 0 of the perimeter of the interface I 0 in the device cross-section is much larger than the correlation length K of the D(s, x) process, which is a very reasonable approximation for most devices of practical interests and for a K in the range of 1 to 2 nm.…”

Section: Modeling Of Surface Roughness Scatteringmentioning

confidence: 99%

“…7,9,11 In particular, for CMOS generations beyond the 7-nm node, gate-all-around (GAA) nanowire FETs appear to be the most promising architecture. 1,2,5,[12][13][14][15] However, nanowire transistors still face significant challenges and, due to the high surface-tovolume ratio, the performance of these devices is strongly influenced by surface roughness (SR) and interface defects. [16][17][18][19][20][21] In this framework, an accurate description of interface effects in order to predict the device performance is required, and the aim of this work is to present a new model for SR scattering in MuGFETs with arbitrary cross-sections.…”

Section: Introductionmentioning

confidence: 99%

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Improved surface-roughness scattering and mobility models for multi-gate FETs with arbitrary cross-section and biasing scheme

Lizzit

Badami

Specogna

et al. 2017

Journal of Applied Physics

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We present a new model for surface roughness (SR) scattering in n-type multi-gate FETs (MuGFETs) and gate-all-around nanowire FETs with fairly arbitrary cross-sections, its implementation in a complete device simulator, and the validation against experimental electron mobility data. The model describes the SR scattering matrix elements as non-linear transformations of interface fluctuations, which strongly influences the root mean square value of the roughness required to reproduce experimental mobility data. Mobility simulations are performed via the deterministic solution of the Boltzmann transport equation for a 1D-electron gas and including the most relevant scattering mechanisms for electronic transport, such as acoustic, polar, and non-polar optical phonon scattering, Coulomb scattering, and SR scattering. Simulation results show the importance of accounting for arbitrary cross-sections and biasing conditions when compared to experimental data. We also discuss how mobility is affected by the shape of the cross-section as well as by its area in gate-all-around and tri-gate MuGFETs. © 2017 Author(s)

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Section: Modeling Of Surface Roughness Scatteringmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Improved surface-roughness scattering and mobility models for multi-gate FETs with arbitrary cross-section and biasing scheme

Lizzit

Badami

Specogna

et al. 2017

Journal of Applied Physics

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“…Hence, it could conceivably be hypothesized that the two recent successful industrial attempts to build NWTs with cross-sectional AR ≈ 1 (circular NWT [8,9] and AR ≈ 3.5 (sheet NWT) [10] have overlooked the fact that AR contributes to NWT performance (in this study, the term "sheet NWT" refers to any NWT where 0.5 ≥ AR ≥ 2). Figure 5 compares the effect of 9 cross-section aspect ratios for Si NWTs on the I D -V G curves.…”

Section: Resultsmentioning

confidence: 99%

“…It is noteworthy that one of the key determinants of device performance has been established as the ratio of the major axis to the minor axis (namely, cross-section aspect ratio or AR). Nevertheless, industrial players have tended to only manufacture NWTs in two different versions: circular cylinder (or elliptical) NWTs [8,9] and nanosheet (or nanoslab) FETs [10]. Each version has its own trade-offs; however, the key difference between these two versions is the cross-sectional AR.…”

Section: Introductionmentioning

confidence: 99%

Correlation between the Golden Ratio and Nanowire Transistor Performance

Al-Ameri

2018

Applied Sciences

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An observation was made in this research regarding the fact that the signatures of isotropic charge distributions in silicon nanowire transistors (NWT) displayed identical characteristics to the golden ratio (Phi). In turn, a simulation was conducted regarding ultra-scaled n-type Si (NWT) with respect to the 5-nm complementary metal-oxide-semiconductor (CMOS) application. The results reveal that the amount of mobile charge in the channel and intrinsic speed of the device are determined by the device geometry and could also be correlated to the golden ratio (Phi). This paper highlights the issue that the optimization of NWT geometry could reduce the impact of the main sources of statistical variability on the Figure of Merit (FoM) of devices. In the context of industrial early successes in fabricating vertically stacked NWT, ensemble Monte Carlo (MC) simulations with quantum correction are used to accurately predict the drive current. This occurs alongside a consideration of the degree to which the carrier transport in the vertically stacked lateral NWTs are complex.

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“…The FinFETs have become the mainstream logic devices for a few nodes [52]. The GAA nano-Si wire FETs and Si nano-sheets FETs have been reported by the research teams using industrial processing facility [53][54][55][56][57][58]. The relation between Vt and the work function of the gate electrode for FinFETs with undoped channel is different to that for the planar MOSFETs.…”

Section: Metal Gate For Finfets and Gaa-fetsmentioning

confidence: 99%

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

Zhao

Xiang

2019

Applied Sciences

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The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

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Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

Cited by 110 publications

References 6 publications

Improved surface-roughness scattering and mobility models for multi-gate FETs with arbitrary cross-section and biasing scheme

Improved surface-roughness scattering and mobility models for multi-gate FETs with arbitrary cross-section and biasing scheme

Correlation between the Golden Ratio and Nanowire Transistor Performance

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

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