FinFET based SRAM design: A survey on device, circuit, and technology issues

Bayoumi, Magdy; Dutta, Anandi

doi:10.1109/icecs.2014.7050003

Cited by 8 publications

(7 citation statements)

References 33 publications

(35 reference statements)

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“…This section discusses about the most recently presented technique for improving the design aspect of FinFET SRAM operation in research area. The conceptual discussion of FinFET SRAM has bulk of research papers and there are some survey papers [14] that has already covered up the discussion of techniques till 2013. However, none of the existing review papers has discussed the comparative analysis of existing techniques with respect to beneficial features and limiting features of existing techniques.…”

Section: Existing Techniquesmentioning

confidence: 99%

“…The study has also investigated about the trends of heat dissipation from the 14nm node to find the temperature reduction capability of 325 K. Study in similar direction was also carried out by Song et al [21] Ansari et al [22] have presented an elaborated study of design improvement of SRAM cells with 7 transistors. The author has considered a simulation-based study with HSPICE using multiple number of transistor (20,16,14, 10, 7 nm). The outcome of the presented simulation study was found to possess better write speed as well as enhanced stability.…”

Section: Existing Techniquesmentioning

confidence: 99%

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Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Girish¹,

Shashikumar²

2016

CAE

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With the advancement in the energy efficient storage system, FinFET has already gained a pace in the area of computational memory management. However, after reviewing the research work focusing on FinFET based SRAM cells till date, we found that amount of research work towards enhancement of the design principle has not been much in number. Hence, we study some of the recently introduced research contribution towards enhancing the design performance of FinFET based SRAM cells and found that majority of the technique have both advantages and limitations too. We also highlights the significant research gap from the existing studies in order to assist the readers aware of the practicality of the research progress in this regards.

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Section: Existing Techniquesmentioning

confidence: 99%

Section: Existing Techniquesmentioning

confidence: 99%

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Girish¹,

Shashikumar²

2016

CAE

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“…Therefore, it has been noticed that various research works have carried towards FinFET based SRAM design by considering the circuit, device and technological challenges and issues [6][7][8]. Also, this paper presents literature work to understand the current trends and the progress of FinFET SRAM technique.…”

Section: Introductionmentioning

confidence: 99%

A novel optimization framework for controlling stabilization issue in design principle of FinFET based SRAM

Girish¹,

R²

2019

IJECE

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The conventional design principle of the finFET offers various constraints that act as an impediment towards improving ther performance of finFET SRAM. After reviewing existing approaches, it has been found that there are not enough work found to be emphasizing on cost-effective optimization by addressing the stability problems in finFET design.Therefore, the proposed system introduces a novel optimization mechanism considering some essential design attributes e.g. area, thickness of fin, and number of components. The contribution of the proposed technique is to determine the better form of thickness of fin and its related aspect that can act as a solution to minimize various other asscoiated problems in finFET SRAM. Implemented using soft-computational approach, the proposed system exhibits that it offers better energy retention, lower delay, and potential capability to offer higher throughput irrespective of presence of uncertain amount of noise within the component.

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“…Authors in [9] discussed the efficacy of various write-assist techniques used in low voltage SRAM. In [10], a short review of FinFET based SRAM is presented that mainly focuses on device issues. Authors in [11] have presented a review of various design challenges and techniques for high performnce SRAM design that covers broad aspects.…”

mentioning

confidence: 99%

“…FIGURE10. Cells with decoupled differential read buffer (a) NOG-D10T[30],[31] (b) SONG-D10T[32] (c) WU-Z8T[33] (d) LIU-D9T[34] (e) KUL-D8T[35] …”

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confidence: 99%

A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

Ahmad¹,

Alam²,

Hasan³

et al. 2022

Preprint

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In order to meet the ultra-low power requirement of modern digital systems, voltage scaling is a fruitful technique that is widely adopted. However, the voltage scaling at ultra-scaled technologies significantly affect the stability of an Static Random Access Memory (SRAM) cell. This work provides an extensive review of various designs and techniques for solving issues related to SRAM cell stability. Decoupling the read operation is a commonly used technique for addressing read stability issue. Modified Schmitt-trigger based cell core, loop-cutting and additional discharge path based techniques have also been employed in the literature to enhance the read stability. However, the write-ability and stability of halfselected (HS) cells have been compromised in some of these technique. For write-ability enhancement, most of the techniques involve either weakening of pull-up/pull-down devices (to reduce the current responsible for storing the data) or strengthening of access transistors (to enhance the write current). It includes VDD/VSS -cut off or -floating, feedback cutting, multi-Vth write assist based cells. Apart from discussing the alternative bitcells, we also cover several peripheral read/write assist techniques. WL underdrive (WLUD) and dynamic WLUD are effective read assist techniques. WL -boost, WL -delayed boost, VDD-floating/lowering, transient VDD collapse, VSS raised, dual split control-VSS raised and negative BL (NBL) are among the peripheral techniques for enhancing write-ability. Furthermore, various techniques for mitigating the HS cell issues, such as write-back, column decoupled local wordline, modified bitinterleaving array architecture are discussed. Finally, the Cross-point selection based cell accessing in-built technique is illustrated. Through summary tables, conclusions are also derived for suggesting a circuit of choice for various categories.

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FinFET based SRAM design: A survey on device, circuit, and technology issues

Cited by 8 publications

References 33 publications

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

A novel optimization framework for controlling stabilization issue in design principle of FinFET based SRAM

A Comprehensive Review of Design Challenges and Techniques for Nanoscale SRAM: A Cell Perspective

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