The scanning capacitance microscope ͑SCM͒ is a carrier-sensitive imaging tool based upon the well-known scanning-probe microscope ͑SPM͒. As reported in Edwards et al. ͓Appl. Phys. Lett. 72, 698 ͑1998͔͒, scanning capacitance spectroscopy ͑SCS͒ is a new data-taking method employing an SCM. SCS produces a two-dimensional map of the electrical pn junctions in a Si device and also provides an estimate of the depletion width. In this article, we report a series of microelectronics applications of SCS in which we image submicron transistors, Si bipolar transistors, and shallow-trench isolation structures. We describe two failure-analysis applications involving submicron transistors and shallow-trench isolation. We show a process-development application in which SCS provides microscopic evidence of the physical origins of the narrow-emitter effect in Si bipolar transistors. We image the depletion width in a Si bipolar transistor to explain an electric field-induced hot-carrier reliability failure. We show two sample geometries that can be used to examine different device properties.
SRAMs are an integral part of system on chip devices. With transistor and gate length scaling to 65nm/45nm nodes, SRAM stability across the product's lifetime has become a challenge. Negative bias temperature instability, defects, or other phenomena that may manifest itself as a transistor threshold voltage (V T ) increase can result in VMIN drift of SRAM memory cells through burn-in and/or operation. A direct assessment at time-zero is difficult because the transistor V T has not yet shifted, and therefore no capability to screen VMIN shift at time zero can be developed. This work describes a methodology developed on 65nm low power and high performance process technologies at Texas Instruments for screening SRAM cells at time zero before they become reliability issues.
IntroductionSRAM reliability on sub-65nm nodes has become a significant challenge. Transistor mis-match at time zero, as well as over the lifetime of a product, could result on memory fails. The screening techniques used to date count on failure mechanisms being present at time zero in order for them to be screened, or they attempt to guard-band products with ranges large enough to contain forecasted shifts. This paper presents a methodology developed on 65nm low power and high performance process technologies at Texas Instruments that is able to screen memory cells that are likely to have stability issues over the lifetime of a product.
Quantitative two-dimensional (2D) dopant profiling for 0.25 micron CMOS technology was demonstrated using secondary ion mass-spectrometry (SIMS) and scanning capacitance spectroscopy (SCS). P-well and N-well dopant profiles measured by 2D SIMS are in agreement with TSUPREM4 (TS4) simulations. TS4 was pre-calibrated to the specific technology using 1D SIMS and electrical data. 2D SIMS, TS4 and SCS show agreement on the well boundary location. SCS is an advanced form of scanning capacitance microscopy (SCM) devised for pn-junction delineation. 2D SIMS dopant profiling with lateral resolution of 10 nm (limited by the lithography pixel size) and sensitivity of 1~1 0 '~ cm" was realized on commercial equipment.
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IntroductionThe goal of this study is to demonstrate capabilities of recently developed two-dimensional (2D) secondary ion mass-spectrometry (SIMS) and scanning capacitance spectroscopy (SCS) techniques for quantitative 2D dopant analysis. SIMS is the only doping characterization technique that directly measures dopant concentration. 2D SIMS was invented by Hill, Dowsett and Cooke (1) and improved lately by using a MoirC pattern design for the test structure (2).
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