0.1 μm RFCMOS on high resistivity substrates for system on chip (SOC) applications

Yang, Jian; Benaissa, K.; Crenshaw, D.; Williams, B.; Sridhar, S.; Ai, Jian; Boselli, Gianluca; Zhao, Siqi; Tang, S. C.; Mahalingam, N.; Ashburn, S.; Madhani, Pankaj M.; Blythe, T.; Shichijo, H.

doi:10.1109/iedm.2002.1175927

Cited by 15 publications

(6 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It has several advantages over bulk silicon for these applications; perhaps most importantly it enables the use of a high resistivity silicon substrate. High resistivity cm silicon reduces substrate RF power loss, conferring considerable benefits to the active and passive elements of an RF system [1]. High resistivity bulk silicon offers the same RF performance advantages as high resistivity SOI, but is believed to pose reliability and yield problems [2], [3].…”

Section: Introductionmentioning

confidence: 99%

RF power performance of an LDMOSFET on high-resistivity SOI

Fiorenza

Alamo

2005

IEEE Electron Device Lett.

View full text Add to dashboard Cite

Abstract-This paper describes the RF power performance of an LDMOSFET technology on high-resistivity silicon-on-insulator wafers. The technology has an on-state breakdown voltage of greater than 10 V, and an off-state breakdown voltage of greater than 20 V. This device technology is shown to have excellent RF power characteristics at frequencies from 1.9 to 5.8 GHz. At 1.9 GHz, a peak power-added efficiency (PAE) of 63% was achieved with an output power of up to 520 mW from a single RF power cell. At 5.8 GHz, a peak PAE of 35% was achieved with an output power of up to 125 mW from a single RF power cell.Index Terms-LDMOSFET, RF power amplifier, silicon-oninsulator (SOI).

show abstract

Section: Introductionmentioning

confidence: 99%

RF power performance of an LDMOSFET on high-resistivity SOI

Fiorenza

Alamo

2005

IEEE Electron Device Lett.

View full text Add to dashboard Cite

show abstract

“…Fig.7 shows a collection of the cut-off frequencies from publications [4,[8][9][10][11][12][13]. It shows that a typical SiGe bipolar transistor inserted two technology nodes behind (less advanced) can offer the same cut-off frequency as CMOS.…”

Section: -5-3mentioning

confidence: 98%

“…Recently, technologies to form global and local high-resistivity silicon region on Silicon substrate are being studied [13][14][15]. One of the promising approaches is to bombard a selected area of the silicon substrate with MeV protons [ 16,171 through a mask, forming a local semi-insulating region -100 pm deep.…”

Section: Substrate and Passivesmentioning

confidence: 99%

Foundry technology for 130nm and beyond SoC

Tang

Diaz

Chao

et al.

Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.

View full text Add to dashboard Cite

Current foundry technology menus are so rich that they are sufficient to provide single chip solutions to a wide variety of desktop, portable and communication systems. At 130-nm and 90-nm generations, many of the device characteristics are no longer a straightfonvard extension ofpast generations [1][2][3][4]. Special attention should be made for mixed-signal chip design. Ajudicious choice of devices and careful trade-off between version options should be made to maximize the benefit from the latest foundry offerings.

show abstract

“…nodes can be reduced by logic. [13,141 Power management is becoming increasingly distributed, especially in low power applications, because of the need to reduce standby power by putting unused logic and memory in a standby or sleep mode. Much of this power management functionality can be accomplished using switches to activate or deactivate blocks of logic.…”

Section: Fig 4: Digital Clock Noise Is Conducted To Sensitive Analog mentioning

confidence: 99%

Cellular handset integration -- SIP vs. SOC

Krenik

Buss

Rickert

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)

View full text Add to dashboard Cite

Cellular handsets are rapidly evolving from voice-only products to highly featured designs featuring color displays, games, audio, video, cameras, Bluetooth, GPS, WLAN, highspeed wide-area data services, and other advanced features. This remarkable expansion in capability, in conjunction with ongoing customer demands for sleek, ergonomic, and reasonably priced handsets with good battery life, places considerable pressure on handset component providers to aggressively integrate the handset electronics. System-in-Package (SIP) integration and Systemon-Chip (SOC) integration are two possible approaches. This paper investigates the tradeoffs between SIP and SOC integration for the integration of memories, analog, and RF electronics in the handset.

show abstract

0.1 μm RFCMOS on high resistivity substrates for system on chip (SOC) applications

Cited by 15 publications

References 9 publications

RF power performance of an LDMOSFET on high-resistivity SOI

RF power performance of an LDMOSFET on high-resistivity SOI

Foundry technology for 130nm and beyond SoC

Cellular handset integration -- SIP vs. SOC

Contact Info

Product

Resources

About