1996
DOI: 10.1117/12.250874
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Study of integration issues in shallow trench isolation for deep submicron CMOS technologies

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“…8 Possible STI process integration schemes have been discussed in some of the early publications. [9][10][11] The focus of this paper is on trench fill using chemical vapor deposited (CVD) SiO 2 film to achieve void-free gap filling capability as well as etch resistance to later process steps, i.e., chemical mechanical polishing (CMP) and HF dip. To date, the available options for such trench fill include ozone/tetraethylorthosilicate (TEOS)-based thermal process using atmospheric pressure, low pressure, and subatmospheric (SA) CVD, and silane-based high-density plasma (HDP) process.…”
mentioning
confidence: 99%
“…8 Possible STI process integration schemes have been discussed in some of the early publications. [9][10][11] The focus of this paper is on trench fill using chemical vapor deposited (CVD) SiO 2 film to achieve void-free gap filling capability as well as etch resistance to later process steps, i.e., chemical mechanical polishing (CMP) and HF dip. To date, the available options for such trench fill include ozone/tetraethylorthosilicate (TEOS)-based thermal process using atmospheric pressure, low pressure, and subatmospheric (SA) CVD, and silane-based high-density plasma (HDP) process.…”
mentioning
confidence: 99%