Integration of unit processes in a shallow trench isolation module for a 0.25 μm complementary metal–oxide semiconductor technology

Abstract

Articles you may be interested inShallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology J. Vac. Sci. Technol. B 28, 391 (2010); 10.1116/1.3359612 Chemical mechanical polishing of shallow trench isolation using the ceria-based high selectivity slurry for sub-0.18 μm complementary metal-oxide-semiconductor fabrication Critical dimension control optimization methodology on shallow trench isolation substrate for sub-0.25 μm technology gate patterning Arsenic doped buried plate characterization in deep trenches for a 0.25 μm complementary metal-oxide-semiconductor technology by chemical etching Round-off of trench corner by post-cylindrical molecular pump sidewall oxidation for 0.25 μm and beyond technologies J.This article presents a study of the issues in integrating the pattern, fill, planarization, and surface cleanup processes to design a shallow trench isolation ͑STI͒ flow suitable for 0.25 m complementary metal-oxide semiconductor technologies. Technological choices and their effects on the characteristics of the STI technology are discussed. Experimental data are presented to illustrate how process choices at various stages of the STI flow are made to optimize the STI structure.

Formation and removal of composite halogenated silicon oxide and fluorocarbon films deposited on chamber walls during plasma etching of multiple film stacks

“…[2][3][4] Traditionally, individual layers were etched in different plasma etching reactors, each dedicated to removing one of the films. However, sequential etching of multiple film stacks in the same chamber is more cost effective and increases productivity.…”

IC layout and manufacturability: critical links and design flow implications

“…3 1 Many foundry density rules still constrain only the average overall feature density on a given layer, rather than local variation in feature density. 2 Current approaches to analysis of layout density do not nd true extremal window densities in the layout.…”

Filling algorithms and analyses for layout density control

“…That is, total empty area outside the bu er distance B from any feature should be scaled by the maximum possible ll density to yield the slack of the window. 6 Note that this is not merely a satis cing formulation where we seek only a feasible solution, but rather an optimization formulation where we seek a best solution, as dictated by the particular underlying VLSI technology.…”

“…Given the parameters above, we de ne the Filling Problem as follows: 6 The Filling Problem. Given a design rule-correct layout geometry of k disjoint rectilinear rectangles in an n n layout region, minimum feature size c, window size w n , bu er distance B, and area or perimeter density l o wer bound L and upper bound U, add ll geometries to create a lled layout that satis es the following conditions:…”