Scanning capacitance spectroscopy (SCS), a variant of scanning capacitance microscopy (SCM), is presented. By cycling the applied dc bias voltage between the tip and sample on successive scan lines, several points of the high-frequency capacitance–voltage characteristic C(V) of the metal–oxide–semiconductor capacitor formed by the tip and oxidized Si surface are sampled throughout an entire image. By numerically integrating dC/dV, spatially resolved C(V) curves are obtained. Physical interpretation of the C(V) curves is simpler than for a dC/dV image as in a single-voltage SCM image, so that the pn junction may be unambiguously localized inside a narrow and well-defined region. We show SCS data of a transistor in which the pn junction is delineated with a spatial resolution of ±30 nm. This observation is consistent with the conclusion that SCS can delineate the pn junction to a precision comparable to the Si depletion width, in other words, the actual size of the electrical pn junction. A physical model to explain the observed SCS data near the pn junction is presented.
The scanning capacitance microscope ͑SCM͒ is a carrier-sensitive imaging tool based upon the well-known scanning-probe microscope ͑SPM͒. As reported in Edwards et al. ͓Appl. Phys. Lett. 72, 698 ͑1998͔͒, scanning capacitance spectroscopy ͑SCS͒ is a new data-taking method employing an SCM. SCS produces a two-dimensional map of the electrical pn junctions in a Si device and also provides an estimate of the depletion width. In this article, we report a series of microelectronics applications of SCS in which we image submicron transistors, Si bipolar transistors, and shallow-trench isolation structures. We describe two failure-analysis applications involving submicron transistors and shallow-trench isolation. We show a process-development application in which SCS provides microscopic evidence of the physical origins of the narrow-emitter effect in Si bipolar transistors. We image the depletion width in a Si bipolar transistor to explain an electric field-induced hot-carrier reliability failure. We show two sample geometries that can be used to examine different device properties.
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