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We have conducted dielectric-breakdown tests on water subject to a single unipolar pulse. The peak voltages used for the tests range from 5.8 to 6.8 MV; the effective pulse widths range from 0.60 to 1:1 s; and the effective areas tested range from 1:8 Â 10 5 to 3:6 Â 10 6 cm 2 . The tests were conducted on waterinsulated coaxial capacitors. Large-area water-insulated electrical components are often incorporated in the designs of multiterawatt pulsedpower accelerators, such as the Z [1-10] and ZR [11] machines. Water-insulated components are also proposed for use in future accelerators [12][13][14][15][16][17][18][19]. Optimizing the design of such an accelerator requires a knowledge of the conditions under which its water-insulated components can be operated reliably.Reference [20] proposes that the characteristic time delay delay between the application of a voltage to a water-insulated anode-cathode gap, and the completion of dielectric failure of that gap, can be approximated as follows:In this expression stat is the statistical component of the delay time; i.e., the characteristic time between the application of the voltage and the appearance of free electrons and ions that initiate the formation of streamers in the water. We define form to be the formative component: the time required for the streamers to propagate across the gap and evolve sufficiently to produce complete dielectric failure.To inhibit electrical breakdown, water-insulated components are usually designed to produce a nominally uniform electric field over most of the component's area. We assume that, when the area of a water-insulated system with a uniform field is sufficiently large, the appearance of free electrons and ions necessary to initiate a breakdown occurs somewhere in the system very early in the voltage pulse [20]. Under this condition the statistical time delay stat can be neglected, and the breakdown delay is dominated by its formative component:In principle, dielectric breakdown dominated by the formative component can be studied with an electrode geometry that consists of a point anode and a planar cathode [20][21][22]. Although measurements with an infinitely field-enhanced anode point and an infinitely extended flat cathode are not possible, a number of dielectric-breakdown measurements between a significantly field-enhanced anode electrode and a less-enhanced cathode have been described in the literature.Using these measurements, Ref.[20] finds that complete dielectric failure is likely to occur in water between a fieldenhanced anode and a less-enhanced cathode when In this expression E p V p =d is the peak value in time of the spatially averaged electric field between the anode and cathode (in MV=cm, where V p is the peak voltage difference and d is the minimum distance between the electrodes), and eff is the temporal width (in s) of the voltage pulse at 63% of peak. This relation is based on 25 measurements for which 1 V p 4:10 MV, 1:25 d 22 cm, and 0:011 eff 0:6 s.To develop a tentative design criterion for a large-area...

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SRAMs are an integral part of system on chip devices. With transistor and gate length scaling to 65nm/45nm nodes, SRAM stability across the product's lifetime has become a challenge. Negative bias temperature instability, defects, or other phenomena that may manifest itself as a transistor threshold voltage (V T ) increase can result in VMIN drift of SRAM memory cells through burn-in and/or operation. A direct assessment at time-zero is difficult because the transistor V T has not yet shifted, and therefore no capability to screen VMIN shift at time zero can be developed. This work describes a methodology developed on 65nm low power and high performance process technologies at Texas Instruments for screening SRAM cells at time zero before they become reliability issues. IntroductionSRAM reliability on sub-65nm nodes has become a significant challenge. Transistor mis-match at time zero, as well as over the lifetime of a product, could result on memory fails. The screening techniques used to date count on failure mechanisms being present at time zero in order for them to be screened, or they attempt to guard-band products with ranges large enough to contain forecasted shifts. This paper presents a methodology developed on 65nm low power and high performance process technologies at Texas Instruments that is able to screen memory cells that are likely to have stability issues over the lifetime of a product.