A 65 nm CMOS technology for mobile and digital signal processing applications

Chatterjee, Amitava; Yoon, Jaegu; Zhao, Song; Tang, S. C.; Sadra, K.; Crank, S.; Mogul, H. C.; Aggarwal, R. J.; Chatterjee, B.; Lytle, S.; Lin, C.; Lee, K.D.; Kim, J.; Hong, Q. Z.; Kim, T.; Olsen, L.; Quevedo‐Lopez, Manuel; Kirmse, K. H. R.; Zhang, G.; Meek, C.; Aldrich, D. B.; Mair, Hugh; Mehrotra, M.; Adam, Lahir Shaik; Mosher, D.; Yang, Jian; Crenshaw, D.; Williams, B.; Jacobs, J.B.; Jain, Mili; Rosal, J.; Houston, T.W.; Wu, Jiesheng; Nagaraj, N.S.; Scott, David B.; Ashburn, S.; Tsao, A.

doi:10.1109/iedm.2004.1419255

Cited by 16 publications

(6 citation statements)

References 2 publications

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“…As discussed in [7], these unity-gain cutoff frequencies obtained on the two wafers characterized in this letter show improvements of 61% and 55% over the literature trend line at 85-nm gate length and even surpass the performance of devices of less than 40-nm gate lengths [9].…”

Section: Resultssupporting

confidence: 55%

High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices

Raskin

Pearman

Pailloncy

et al. 2008

IEEE Electron Device Lett.

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Abstract-A radio-frequency performance of 85-nm gate-length p-type Schottky barrier (SB) with PtSi source/drain materials is investigated. The impact of silicidation annealing temperature on the high-frequency behavior of SB MOSFETs is analyzed using an extrinsic small-signal equivalent circuit. It is demonstrated that the current drive and the gate transconductance strongly depend on the silicidation anneal temperature, whereas the unity-gain cutoff frequency of the measured devices remains nearly unchanged.Index Terms-Electrostatic measurement, microwave measurements, SB metal/source MOSFETs, scattering parameter measurement, Schottky barriers (SBs), semiconductor devices.

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Section: Resultssupporting

confidence: 55%

High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices

Raskin

Pearman

Pailloncy

et al. 2008

IEEE Electron Device Lett.

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“…Our technology model is intended to be representative of the 65nm processes disclosed in [2,3,13]. Device models are based on the predictive technology models described in [22].…”

Section: Technology Modelmentioning

confidence: 99%

“…Device models are based on the predictive technology models described in [22]. Interconnect models were derived from [10,2,3,13]. Tables 1 and 2 present relevant parameters.…”

Section: Technology Modelmentioning

confidence: 99%

Design tradeoffs for tiled CMP on-chip networks

Balfour

Dally

2006

Proceedings of the 20th Annual International Conference on Supercomputing

432

300

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We develop detailed area and energy models for on-chip interconnection networks and describe tradeoffs in the design of efficient networks for tiled chip multiprocessors. Using these detailed models we investigate how aspects of the network architecture including topology, channel width, routing strategy, and buffer size affect performance and impact area and energy efficiency. We simulate the performance of a variety of on-chip networks designed for tiled chip multiprocessors implemented in an advanced VLSI process and compare area and energy efficiencies estimated from our models. We demonstrate that the introduction of a second parallel network can increase performance while improving efficiency, and evaluate different strategies for distributing traffic over the subnetworks. Drawing on insights from our analysis, we present a concentrated mesh topology with replicated subnetworks and express channels which provides a 24% improvement in area efficiency and a 48% improvement in energy efficiency over other networks evaluated in this study.

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“…Layer thicknesses vary greatly. For instance, on a 7 metal 65 nm Texas Instruments (TI) [4] baseband processor chip we recently analyzed (Figure 12), we found:…”

Section: Circuit Extractionmentioning

confidence: 99%

The State-of-the-Art in IC Reverse Engineering

Torrance

James

2009

Lecture Notes in Computer Science

267

132

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Abstract. This paper gives an overview of the place of reverse engineering (RE) in the semiconductor industry, and the techniques used to obtain information from semiconductor products.The continuous drive of Moores law to increase the integration level of silicon chips has presented major challenges to the reverse engineer, obsolescing simple teardowns, and demanding the adoption of new and more sophisticated technology to analyse chips. Hardware encryption embedded in chips adds a whole other level of difficulty to IC analysis. This paper covers product teardowns, and discusses the techniques used for system-level analysis, both hardware and software; circuit extraction, taking the chip down to the transistor level, and working back up through the interconnects to create schematics; and process analysis, looking at how a chip is made, and what it is made of. Examples are also given of each type of RE. The paper concludes with a case study of the analysis of an IC with embedded encryption hardware.

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A 65 nm CMOS technology for mobile and digital signal processing applications

Cited by 16 publications

References 2 publications

High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices

High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices

Design tradeoffs for tiled CMP on-chip networks

The State-of-the-Art in IC Reverse Engineering

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