Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher oncurrents of n- and p-TFETs of >10 μA/μm at VDS = 0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very low VDD = 0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD = 1.0 V

The Schottky barrier height ͑SBH͒ of NiSi on Si͑100͒ was tuned in a controlled manner by the segregation of sulfur ͑S͒ to the silicide/silicon interface. S was implanted into silicon prior to silicidation. During subsequent Ni silicidation, the segregation of S at the NiSi/ Si interface leads to the change of the SBH. The SBH of NiSi decreased gradually on n-Si͑100͒ from 0.65 eV to 0.07 eV and increased correspondingly on p-Si͑100͒. © 2005 American Institute of Physics. ͓DOI: 10.1063/1.1863442͔ Self-aligned silicidation is one of the key technologies in the state-of-art complementary metal-oxide-semiconductor ͑CMOS͒ process to make Ohmic or Schottky contacts at source/drain and gate. Amongst of them, NiSi silicide has emerged as a leading choice in Si nanometer electronics due to its low resistivity and high scalability. Recently, Schottky barrier source/drain metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒ have been receiving a lot of attention because of the lower parasitic series resistance at source/ drain, possible zero junction depth and simpler fabrication process.1-4 However, for a typical Schottky barrier ͑SB͒ MOSFET, the on-current is limited by the tunneling through the Schottky barrier at the source. If a very low or a negative SBH could be realized, the on-current of SB-MOSFET could be increased substantially. 4 NiSi has an experimental SBH of 0.65 eV on n-Si͑100͒. This high SBH value hinders the application of NiSi in SB-MOSFETs. If we can lower the SBH of silicides to very low value, the device exhibits the same intrinsic performance as conventional MOSFET but also benefits from the advantages of SB-MOSFETs mentioned above.In an ideal metal-semiconductor system the SchottkyMott theory suggests that the SBH ͑⌽ B ͒ is simply determined by the difference between the work function of the metal ͑ M ͒ and the electron affinity of the semiconductor5 In practice, however, the presence of interface states leads to the SBH being less dependent on the metal work function. Dangling bonds at the semiconductor surface can be eliminated by valence-mending adsorbates. 6 S and Se are two possible valence-mending candidates for the Si͑100͒ surface.6 Lacharme et al. 7 reported that surface states on Si can be removed by S exposure at room temperature. Tao et al. [8][9][10] have used a monolayer of Se to eliminate the surface states on the Si͑001͒ surface by terminating dangling bond and relaxing strained bonds. Pure metals, like Mg, Al, Cr, and Ti, on Se-passivated n-Si͑001͒ showed very low and even negative SBH values which can be predicted by the Schottky-Mott theory.8-10 However, deposition of these elements seems inappropriate for silicide contacts on Si due to the suppression of silicide formation. 10 In order to benefit from advantages of silicides in state-of-art MOSFET technology, methods to tune the SBH of silicides on Si are required. In this paper we show an effective method to tune the SBH value of NiSi on both n-and p-type Si͑100͒. A small dose of S ions was implanted into Si before Ni de...

Artificial synapses based on ferroelectric Schottky barrier field-effect transistors (FE-SBFETs) are experimentally demonstrated. The FE-SBFETs employ single-crystalline NiSi2 contacts with an atomically flat interface to Si and Hf0.5Zr0.5O2 ferroelectric layers on silicon-on-insulator substrates. The ferroelectric polarization switching dynamics gradually modulate the NiSi2/Si Schottky barriers and the potential of the channel, thus programming the device conductance with input voltage pulses. The short-term synaptic plasticity is characterized in terms of excitatory/inhibitory post-synaptic current (EPSC) and paired-pulse facilitation/depression. The EPSC amplitude shows a linear response to the amplitude of the pre-synaptic spike. Very low energy/spike consumption as small as ∼2 fJ is achieved, demonstrating high energy efficiency. Long-term potentiation/depression results show very high endurance and very small cycle-to-cycle variations (∼1%) after 105 pulse measurements. Furthermore, spike-timing-dependent plasticity is also emulated using the gate voltage pulse as the pre-synaptic spike and the drain voltage pulse as the post-synaptic spikes. These findings indicate that FE-SBFET synapses have high potential for future neuromorphic computing applications.

This letter reports for the first time a full experimental study of performance boosting of Tunnel FETs (TFETs) and MOSFETs by Negative Capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capacitance to achieve hysteretic and non-hysteretic characteristics. PZT ferroelectric capacitors are connected to the gate of three terminals TFETs and MOSFETs and partial or full matching NC conditions for amplification and stability are obtained. First, we demonstrate characteristics of hysteretic and non-hysteretic NC-TFETs. The main performance boosting is obtained for the non-hysteretic NC-TFET, where the on-current is increased by a factor of 500x, transconductance is enhanced by three orders of magnitude, and the low slope region is extended. The boosting of performance is moderate in the hysteretic NC-TFET. Second, we investigate the impact of the same NC booster on MOSFETs. Subthreshold swing as steep as 4mV/dec with a 1.5V hysteresis is obtained on a commercial device fabricated in 28nm CMOS technology. Moreover, we demonstrate a nonhysteretic NC-MOSFET with a full matching of capacitances and a reduced subthreshold swing down to 20mV/dec.

We present an investigation of the use of dopant segregation in Schottky-barrier metal-oxide-semiconductor field-effect transistors on silicon-on-insulator. Experimental results on devices with fully nickel silicided source and drain contacts show that arsenic segregation during silicidation leads to strongly improved device characteristics due to a strong conduction/valence band bending at the contact interface induced by a very thin, highly doped silicon layer formed during the silicidation. With simulations, we study the effect of varying silicon-on-insulator and gate oxide thicknesses on the performance of Schottky-barrier devices with dopant segregation. It is shown that due to the improved electrostatic gate control, a combination of both ultrathin silicon bodies and gate oxides with dopant segregation yields even further improved device characteristics greatly relaxing the need for low Schottky barrier materials in order to realize high-performance Schottky-barrier transistors.

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Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursued approaches to achieve such a subthermionic subthreshold swing consist in alternative carrier injection mechanisms, like quantum mechanical band-to-band tunneling (BTBT) in Tunnel FETs or abrupt phase-change in metal-insulator transition (MIT) devices. The strengths of the BTBT and MIT have been combined in a hybrid device architecture called phase-change tunnel FET (PC-TFET), in which the abrupt MIT in vanadium dioxide (VO2) lowers the subthreshold swing of strained-silicon nanowire TFETs. In this work, we demonstrate that the principle underlying the low swing in the PC-TFET relates to a sub-unity body factor achieved by an internal differential gate voltage amplification. We study the effect of temperature on the switching ratio and the swing of the PC-TFET, reporting values as low as 4.0 mV/decade at 25 °C, 7.8 mV/decade at 45 °C. We discuss how the unique characteristics of the PC-TFET open new perspectives, beyond FETs and other steep-slope transistors, for low power electronics, analog circuits and neuromorphic computing.

Ultrathin Ni silicides were formed on silicon-oninsulator (SOI) and biaxially tensile strained SOI (SSOI) substrates. The Ni layer thickness crucially determines the silicide phase formation: With a 3-nm Ni layer, high-quality epitaxial NiSi 2 layers were grown at temperatures > 450 • C, while NiSi was formed with a 5-nm-thick Ni layer. A very thin Pt interlayer, to incorporate Pt into NiSi, improves the thermal stability and the interface roughness and lowers the contact resistivity. The contact resistivity of epitaxial NiSi 2 is about one order of magnitude lower than that of a NiSi layer on both As-and B-doped SOI and SSOI.