In this work, we propose and investigate the high performance and low power design space of non-hysteretic negative capacitance MOSFETs for the 14 nm node based on the calibrated simulations using an experimental gate stack with PZT ferroelectric to obtain negative capacitance effect. All necessary parameters are extracted by carefully characterizing experimentally fabricated ferroelectric capacitors, to ensure realistic simulation results. The ferroelectric thickness obtained by the proposed approach leads to the maximum enhancement in the non-hysteretic operation of negative capacitance transistors. We report a clear and significant double improvement in (i) subthreshold swing and (ii) gate overdrive, using negative capacitance effect. Simulations using Silvaco TCAD coupled with a realistic Landau model of ferroelectrics demonstrates that a 14 nm node UTBB FDSOI-FET can operate at 0.26 V instead of 0.9 V gate voltage using negative capacitance effect, with an average subthreshold swing of 55 mV/decade at room temperature. The double gate structure is proposed to overcome the large mismatch between the ferroelectric and MOS capacitor to enhance the negative capacitance effect and reduce the ferroelectric's optimized thickness. A 14 nm node DG-NCFET can operate at 0.24 V gate voltage with an average subthreshold swing of 45 mV/decade.
This letter reports for the first time a full experimental study of performance boosting of Tunnel FETs (TFETs) and MOSFETs by Negative Capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capacitance to achieve hysteretic and non-hysteretic characteristics. PZT ferroelectric capacitors are connected to the gate of three terminals TFETs and MOSFETs and partial or full matching NC conditions for amplification and stability are obtained. First, we demonstrate characteristics of hysteretic and non-hysteretic NC-TFETs. The main performance boosting is obtained for the non-hysteretic NC-TFET, where the on-current is increased by a factor of 500x, transconductance is enhanced by three orders of magnitude, and the low slope region is extended. The boosting of performance is moderate in the hysteretic NC-TFET. Second, we investigate the impact of the same NC booster on MOSFETs. Subthreshold swing as steep as 4mV/dec with a 1.5V hysteresis is obtained on a commercial device fabricated in 28nm CMOS technology. Moreover, we demonstrate a nonhysteretic NC-MOSFET with a full matching of capacitances and a reduced subthreshold swing down to 20mV/dec.
Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.
a b s t r a c tThe implementation and operation of the nonvolatile ferroelectric memory (NVM) tunnel field effect transistors with silicon-doped HfO 2 is proposed and theoretically examined for the first time, showing that ferroelectric nonvolatile tunnel field effect transistor (Fe-TFET) can operate as ultra-low power nonvolatile memory even in aggressively scaled dimensions. A Fe-TFET analytical model is derived by combining the pseudo 2-D Poisson equation and Maxwell's equation. The model describes the Fe-TFET behavior when a time-dependent voltage is applied to the device with hysteretic output characteristic due to the ferroelectric's dipole switching. The theoretical results provide unique insights into how device geometry and ferroelectric properties affect the Fe-TFET transfer characteristic. The recently explored ferroelectric, silicon-doped HfO 2 is employed as the gate ferroelectric. With the ability to engineer ferroelectricity in HfO 2 thin films, a high-K dielectric well established in memory devices, the silicon-doped HfO 2 opens a new route for improved manufacturability and scalability of future 1-T ferroelectric memories. In the current research, a Si:HfO 2 based Fe-TFET with large memory window and low power dissipation is designed and simulated. Utilizing our presented model, the device characteristics of a Fe-TFET that takes full benefits from Si:HfO 2 is compared with the same devices using well-known perovskite ferroelectrics. Finally, the Fe-TFET is compared with a conventional ferroelectric memory transistor highlighting the advantages of using tunneling memory devices.
In this paper, we report a detailed study of the negative capacitance field effect transistor (NCFET). We present the condition for the stabilization of the negative capacitance to achieve the voltage amplification across the active layer. The theory is based on Landauʼs theory of ferroelectrics combined with the surface potential model in all regimes of operation. We demonstrate the validity of the presented theory on experimental NCFETs using a gate stack made of P(VDF-TrFE) and SiO 2 . The proposed analytical modeling shows good agreement with experimental data.
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