Artificial Synapses Based on Ferroelectric Schottky Barrier Field-Effect Transistors for Neuromorphic Applications

Abstract

Artificial synapses based on ferroelectric Schottky barrier field-effect transistors (FE-SBFETs) are experimentally demonstrated. The FE-SBFETs employ single-crystalline NiSi2 contacts with an atomically flat interface to Si and Hf0.5Zr0.5O2 ferroelectric layers on silicon-on-insulator substrates. The ferroelectric polarization switching dynamics gradually modulate the NiSi2/Si Schottky barriers and the potential of the channel, thus programming the device conductance with input voltage pulses. The short-term synaptic plasticity is characterized in terms of excitatory/inhibitory post-synaptic current (EPSC) and paired-pulse facilitation/depression. The EPSC amplitude shows a linear response to the amplitude of the pre-synaptic spike. Very low energy/spike consumption as small as ∼2 fJ is achieved, demonstrating high energy efficiency. Long-term potentiation/depression results show very high endurance and very small cycle-to-cycle variations (∼1%) after 105 pulse measurements. Furthermore, spike-timing-dependent plasticity is also emulated using the gate voltage pulse as the pre-synaptic spike and the drain voltage pulse as the post-synaptic spikes. These findings indicate that FE-SBFET synapses have high potential for future neuromorphic computing applications.

Biocompatible Casein Electrolyte-Based Electric-Double-Layer for Artificial Synaptic Transistors

“…Figure 6 b shows the calculated ∆ W , which is represented by dots. The result exhibits asymmetric Hebbian learning STDP characteristics, which is one of the biological STDP functions [ 49 ]. When |Δ t | decreased, synaptic weights were strengthened during the post-synaptic spike process after the pre-synaptic spike (Δ t > 0), resulting in LTP.…”

Proton gated oxide neuromorphic transistors with bionic vision enhancement and information decoding

“…To date, several kinds of neuromorphic devices have been proposed, including two-terminal memristors [5][6][7] and three-terminal transistors. [8][9][10][11][12][13][14] Additionally, multi-terminal memristors and memtransistors have also been proposed, resulting in the emulation of advanced synaptic functions, including synaptic competition and synaptic cooperation, heterosynaptic plasticity, etc. [15][16][17] Moreover, advanced neural functions have also been mimicked, including image memory, 11,18 pattern recognition, 19 reservoir computation, 20 classical conditioned reflex, 21,22 etc.…”

Tunable Linearity of Weight Update in Low Voltage Synaptic Transistors with Periodic High‐k Laminates

“…[ 18 ] However, the accumulated charges (holes/electrons) tend to be dissipated quickly after low‐voltage operations, and reach a saturation state with improved voltages, which lead to the nonlinear behavior of the conductance switching. [ 11,19 ] The demanded nonvolatile and reliable multi‐level date storage properties promote the implementation of nanoparticle floating gate synaptic transistors. [ 20 ] The charge carriers are injected into discretely distributed floating gates with good retention behavior, since the floating gates are completely surrounded by insulating blocking and tunneling dielectric layers.…”

“…[7][8][9] Synaptic transistor provides a parallel "write" and "read" operation through the gating of channel conductance by the dielectrics, including electret, ferroelectric, ionic, and floating gate, etc. [10][11][12][13][14][15][16] Accordingly, it has the ability of completing the signal transmission and learning process synchronously for the simulating of synaptic functionalities. [17] Charge storage dielectrics have attracted considerable attention in synaptic transistors, due to the rich material sources, simple procedure, and wide process window.…”

“…[18] However, the accumulated charges (holes/electrons) tend to be dissipated quickly after low-voltage operations, and reach a saturation state with improved voltages, which lead to the nonlinear behavior of the conductance switching. [11,19] The demanded nonvolatile and reliable multi-level date storage Synaptic transistors have shown great potential in neuromorphic computing, but remain challenging to simulate linear weight updates through conductance switching under low voltage spiking operation. Here, a low voltage and near-linear weight update synaptic transistor are proposed by developing an interfacial-defect dominated floating gate structure, in which inter-diffused defects are surrounded by near-defect free and ultrathin (1 nm) dielectrics in HfO 2 /Al 2 O 3 periodic high-k laminates.…”