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A novel memory cell for phase-change memories (PCMs) that enables low-power operation has been developed. Power (i.e., current and voltage) for the cell is significantly reduced by inserting a very thin Ta 2 O 5 film between GeSbTe (GST) and a W plug. The Ta 2 O 5 interfacial layer works not only as a heat insulator enabling effective heat generation in GST but also as an adhesion layer between GST and SiO 2 underneath. Nonetheless, sufficient current flows through the interfacial layer due to direct tunneling. A low programming power of 1.5 V/100 µA can therefore be obtained even on a W plug with a diameter of 180 nm fabricated using standard 0.13-µm CMOS technology. In addition, the uniformity and repeatability of cell resistance are excellent because of the inherently stable Ta 2 O 5 film properties.

A three-dimensional (3-D) vertical chain-cell-type phase-change memory (VCCPCM) for next-generation large-capacity storage was developed. The VCCPCM features formation of memory holes in multi-layered stacked gates by using a single mask and a memory array without a selection transistor. As a result of this configuration, the number of process steps for fabricating the VCCPCM is reduced. The excellent scalability of the VCCPCM's new phase-change material makes it possible to reduce the cell size beyond the scaling limit of flash memory. In addition, a poly-silicon selection diode makes it possible to reduce the cell factor to 4F 2 . Consequently, relative cost of the VCCPCM compared to 3-D flash memory is reduced to 0.2. IntroductionThe most important requirement for the storage-memory market is reduction of bit cost, and that requirement has been met by reducing the cell size of flash memory. However, high-voltage operation of flash memory makes it difficult to further reduce cell size. It has recently been reported that the bit-cost reduction can be continued by utilizing 3-D flash memory [1]. 3-D flash memory needs fewer process steps compared to simple stacking of flash memory, but reducing cell size is difficult for two reasons. Firstly, a 20-nm-thick ONO layer in the memory hole is needed and, secondly, a vertical poly-silicon selection MOS transistor needs a cell factor of 6F 2 [1]. In this work, a vertical chain-cell-type phase-change memory (VCCPCM), which can overcome these problems concerning 3-D flash in view of bit cost, is proposed. The key technologies of this VCCPCM are (1) a vertical chain cell for reducing the number of process steps, (2) a scalable new phase-change material for reducing cell size, and (3) a poly-Si XY-selection diode for reducing cell factor to 4F 2 . A poly-Si diode [2] and a lateral chain-cell-type PCM [3] were previously developed. Relative bit cost of both 3-D flash memory and VCCPCM is shown in Fig. 1. By virtue of technologies (1) to (3), the relative bit cost of the VCCPCM compared to 3-D flash memory is reduced to 0.2. Table 1 compares characteristics of 3-D flash memory and VCCPCM. In the present study, set, reset, and reading operations of the VCCPCM were confirmed. Moreover, off-current variation of the poly-Si diode was suppressed by short-time annealing.2. Device structure and operation method The structure of the VCCPCM is shown in Fig. 2. The poly-Si selection diode and VCCPCM are connected serially and positioned at the cross points between the bit and word lines. The structure and equivalent circuit of a VCCPCM are shown in Fig. 3. The gate oxide, channel poly-silicon, and the phase-change material are formed on the side of the holes in the stacked gates. Each memory cell consists of a poly-silicon transistor and a phase-change layer connected in parallel. The memory cells are connected serially in the vertical direction. In the set/reset operations, an off-voltage is applied to the gate at the selected cell, and a positive on-voltage is applied to the unselect...

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d Toho Engineering Company, Yokkaichi, Mie, JapanReal-time coefficient of friction ͑COF͒ analysis was used to determine the extent of normal and shear forces during chemical mechanical planarization ͑CMP͒ and identify the lubrication mechanism of the process. Experiments were done on a scaled polisher using IC-1000 pads with various surface textures, and Fujimi's PL-4217 fumed silica slurry over a wide range of applied pressures and relative pad-wafer velocities. Stribeck curves showed that pad texture dictated the overall lubrication mechanism of the system. Average COF results yielded valuable information regarding the overall range of frictional forces associated with each type of surface texture. The linear correlation between COF data and interlayer dielectric ͑ILD͒ removal rate was consistent with previously published correlation graphs involving a variety of conventional pad textures and fumed silica concentrations. Spectral analysis of real-time friction data was used to elucidate the lubrication mechanism of the process in terms of the stick-slip phenomena and to quantify the total amount of hydrodynamic chattering as a function of various pad surface textures. For a given lubrication mechanism, analysis of the spectra for various textures indicated significant differences that were attributed to the amount of slurry present in the pad-wafer interface.Chemical mechanical planarization ͑CMP͒ has played an enabling role in attaining planar interconnection and metal layers essential for the realization and miniaturization of high-performance devices. To ensure stable and high-performance CMP characteristics, optimization of the slurry and the pad in terms of their chemical and mechanical properties is essential. Furthermore, understanding and optimizing the interactions between the pad and the slurry are important as they relate to the fluid dynamics of the process ͑espe-cially for 300 mm wafers͒ where the need to ͑i͒ minimize slurry dispense volumes, (ii) attain uniform slurry flow, (iii) discharge debris generated during polishing ͑such as pad fragments and polish by-products͒ and (iv) prevent subsequent particle redeposition are paramount. 1 Another key attribute resulting from the interactions between the slurry and the pad is the magnitude of shear forces in the pad-slurry-wafer region associated with a given set of process and consumable parameters. While increasing shear force ͑or frictional force͒ is shown to increase material removal rates, 2,3 high amounts of force can adversely affect the quality of the processed wafers by increasing the number of defects generated during the process 4 and by causing delamination of the underlying insulating films ͑especially low-strength porous or organic low k dielectrics͒. 5 Given the fact that shear force is the product of downforce and the coefficient of friction, the magnitude of shear force can be reduced by either reducing the wafer pressure, or by reducing the coefficient of friction in the pad-slurry-wafer region. The former method can be quite a costly...

The superlattice film with the periodical thin film layers of Sb2Te3/GeTe used as a phase change memory was studied for deposition in the crystal phase. We successfully fabricated the superlattice structure with the sputtering temperature of 200 °C. Moreover, the pillar structure with the size of 70 nm was dry-etched using a HBr/Ar gas mixture.

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