Ta2O5 Interfacial Layer between GST and W Plug enabling Low Power Operation of Phase Change Memories

Abstract

A novel memory cell for phase-change memories (PCMs) that enables low-power operation has been developed. Power (i.e., current and voltage) for the cell is significantly reduced by inserting a very thin Ta 2 O 5 film between GeSbTe (GST) and a W plug. The Ta 2 O 5 interfacial layer works not only as a heat insulator enabling effective heat generation in GST but also as an adhesion layer between GST and SiO 2 underneath. Nonetheless, sufficient current flows through the interfacial layer due to direct tunneling. A low programming power of 1.5 V/100 µA can therefore be obtained even on a W plug with a diameter of 180 nm fabricated using standard 0.13-µm CMOS technology. In addition, the uniformity and repeatability of cell resistance are excellent because of the inherently stable Ta 2 O 5 film properties.

The Role of Interfaces in Damascene Phase-Change Memory

“…Damascene-GST cell required to generate Joule heat, research has focused on reducing reset current by creating a small contact area [2,3] To build the cell, a double-spacer and etch-back technique such as in a Lance cell (Fig. 1) or notably by adding an has been developed with attention to how regions can be interface material [4].…”

Electrical switching dynamics in circular and rectangular Ge2Sb2Te5 nanopillar phase change memory devices

“…Following the original work of Ovshinsky 1 , the reversible switching phenomena observed in disordered semiconductors has attracted substantial theoretical 2,3,4,5,6,7 and experimental 8,9,10,11,12,13 efforts targeted at gaining a deep understanding of the physical principles that govern the switching dynamics, and also learning how to control and optimize the power requirements coupled with characteristic switching timescales. Dramatic and ultra-fast (nanosecond scale) changes in the physical properties such as electrical resistivity and optical reflectivity upon amorphization or crystallization makes chalcogenides ideal potential candidates for a universal non-volatile memory device, especially if, the device switching characteristics are highly scalable to nanometer dimensions.…”

EFFECTS OF BARRIER LAYERS ON THE ELECTRICAL BEHAVIORS OF PHASE-CHANGE MEMORY DEVICES USING Sb-RICH Ge-Sb-Te FILMS

“…Although Hitachi has used a very thin Ta 2 O 5 layer as an adhesion-promoting and heat-insulating layer between GST and bottom electrode contact [10], the insertion of thin dielectric layer between TEC and phase-change material is the first trial to our knowledge. Introduced Al 2 O 3 layer can be expected to act as an effective passivation layer protecting Ge-SbTe alloy from aging in an operating ambient as well as a proposed diffusion barrier.…”