We demonstrated the operation of phase-change memory cells that enabled 1.

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A novel memory cell for phase-change memories (PCMs) that enables low-power operation has been developed. Power (i.e., current and voltage) for the cell is significantly reduced by inserting a very thin Ta 2 O 5 film between GeSbTe (GST) and a W plug. The Ta 2 O 5 interfacial layer works not only as a heat insulator enabling effective heat generation in GST but also as an adhesion layer between GST and SiO 2 underneath. Nonetheless, sufficient current flows through the interfacial layer due to direct tunneling. A low programming power of 1.5 V/100 µA can therefore be obtained even on a W plug with a diameter of 180 nm fabricated using standard 0.13-µm CMOS technology. In addition, the uniformity and repeatability of cell resistance are excellent because of the inherently stable Ta 2 O 5 film properties.

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This paper describes a text-ranking system developed by bunji team in SemEval-2017 Task 3: Community Question Answering, Subtask A and C. The goal of the task is to re-rank the comments in a question-andanswer forum such that useful comments for answering the question are ranked high. We proposed a method that combines neural similarity features and handcrafted comment plausibility features, and we modeled inter-comments relationship using conditional random field. Our approach obtained the fifth place in the Subtask A and the second place in the Subtask C.

Phase-change memory is promising because it has a simple structure and has scalability that originates from its unique operating mechanism. However, the programming current should be reduced in accordance with the scaling of cell size [1,2]. We previously reported PCM (Phase Change Memory) cells that operate under 1.5-V/100-µA writing pulses [3,4]. This PCM had a cell structure composed of 180-nm-W (tungsten) bottom contact to an O-GST (Oxygen-doped GeSbTe) film. Its low-power characteristic is suitable for 0.13-µm generation embedded applications. In the present study, we introduced a new W/O-GST/TaO/W cell structure and found further decrease of programming current the improved stability in the fabrication process. We analyzed the mechanism by which oxygen in GST and the additional TaO layer reduce the power consumption during SET/RESET operations.A memory cell was composed of a cell-selection MOS transistor with a 0.48-µm gate width and a PCM diode. The cross section of the fabricated cell is shown in Fig. 1. The oxygen doping level to the GeSbTe film in this cell was 4.2%. Typical reset current of 100 µA was achieved with an W/O-GST/W structure that is almost 100 times smaller than those for the W/pure-GST/W structure [3]. The programming conditions of a PCM cell used were as follows; the bit-line voltages during the pulse application were 1.4 V for RESET operations and 1.2 V for SET operations, the durations of the pulses were 100 ns for RESET and 10 µs for SET operations. In order to improve the fabrication process stability, we introduced a 2-nm-thick TaO adhesion layer between an O-GST film and a W plug electrode. The SET and RESET characteristics of this W/O-GST/TaO/W structure cell are shown in Fig. 2. As is shown in Fig. 2, the smallest RESET current of 55 µA was achieved with this PCM cell. This low RESET current may be attributable to the thermal confinement caused by the TaO layer [4].

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