The electrical stability of CMOS devices with conventional gate dielectrics is commonly studied using static (DC) measurement techniques. By applying the same methods to MOS devices with alternative gate dielectrics, it has been shown that alternative gate stacks suffer from severe charge trapping and that the trapped charge is not stable, leading to fast transient charging components. In this paper timeresolved measurement techniques down to the p time range are applied to capture the fast transient component of the charge trapping observed in SiO, I Hf02 dual layer gate stacks. Furthermore, its impact on the device performance and reliability of n-channel FETs is discussed.

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