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High-k stacks will be used in Flash memory cells for technology beyond sub-30 nm generations. Abnormal window shift during memory operations has been observed and was attributed to trapping/detrapping of electrons or dielectric relaxation in the high-k layer. In this work, the cause of abnormal V TH /V FB shift at low operating electric fields is investigated. For the first time, extensive experimental evidences show that this shift is caused by as-grown mobile charges in Al 2 O 3 layers. Its impacts on program/erase windows and read/pass disturbance in Flash memory cells are evaluated.

This work gives a review of the recent progress in understanding the instability and defects in gate dielectrics. It consists of two parts: electron-trapping for nMOSFETs and positive charging for pMOSFETs. On electron traps, the issues addressed include the relation between conduction mechanism and trap-filling, the capture cross section, location and sensitivity to fabrication techniques. On positive charging, a framework is proposed for the defect and the unique impact of each type of defect on device performance will be shown. Finally, the progress in NBTI measurement will be highlighted.