Statistical characterization of vertical poly-Si channel using charge pumping technique for 3D flash memory optimization

Tang, Bao-Jun; Toledano-Luque, M.; Zhang, W.D.; bosch, G. Van den; Degraeve, R.; Zhang, J.F.; Houdt, J. Van

doi:10.1016/j.mee.2013.03.067

Cited by 11 publications

(4 citation statements)

References 6 publications

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“…Among the many known problems (too harsh etching process difficulty, mechanical stress, etc. ), the biggest problem is the increase in leakage current due to the internal trap of polysilicon, a channel material, the scattering of threshold voltages, and changes in operating current according to temperature [5,6]. As described above, various studies are being conducted to solve various problems that occur in polysilicon channels because they are fatal to the operation of 3D NAND flash.…”

Section: Introductionmentioning

confidence: 99%

An Improved Structure Enabling Hole Erase Operation When Using an IGZO Channel in a 3D NAND Flash Structure to Which COP (Cell-On-Peri) Structure Is Applied

2023

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In this paper, we proposed an improved (Indum-Galum-Zinc-Oxide) IGZO-Filler (IF) structure that can be used in a Cell-On-Peri (COP) structure by improving the excellent erase performance of the IGZO-Pillar (IP) structure. The IP structure mentioned above is a structure that we announced in a previous study, and this structure overcomes the poor hole carrier characteristics of IGZO when the IGZO channel was used in the early 3D NAND Flash structure and enables hole erase operation. The proposed structure showed that, despite the very poor hole carrier characteristics of IGZO, hole erase operation is sufficiently possible even if only a few hole carriers exist in a thin pillar of 5 nm thickness. Simulation results show that the proposed structure exhibits a fast erase rate of 100 μs, similar to that of the existing structure, while maintaining the low leakage current properties inherent in the IGZO material. Therefore, the proposed structure is expected to maintain the excellent characteristics of the IGZO channel even in the 3D NAND Flash of the COP structure, which enables erasure operation while overcoming leakage current and temperature stability problems of existing polysilicon channels.

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Section: Introductionmentioning

confidence: 99%

An Improved Structure Enabling Hole Erase Operation When Using an IGZO Channel in a 3D NAND Flash Structure to Which COP (Cell-On-Peri) Structure Is Applied

2023

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“…As is widely known, crystallized silicon channels cannot be utilized in 3D NAND flash structures due to process limitations, leading to the adoption of polycrystalline silicon channels. However, a number of electrical problems have been reported in these polysilicon channels due to the presence of grain boundaries within the numerous amorphous structures and the traps found in the channels [8,9].…”

Section: Introductionmentioning

confidence: 99%

An Optimized Device Structure with Improved Erase Operation within the Indium Gallium Zinc Oxide Channel in Three-Dimensional NAND Flash Applications

Choi,

Park,

Kang

et al. 2024

Electronics

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In this paper, we propose an optimized device structure to address issues in 3D NAND flash memory devices, which encounter difficulties when using the hole erase method due to the unfavorable hole characteristics of indium gallium zinc oxide (IGZO). The proposed structure mitigated the erase operation problem caused by the low hole mobility of IGZO by introducing a filler inside the IGZO channel. It facilitated the injection of holes into the IGZO channel through the filler, while the existing P-type doped polysilicon filler material was replaced by a P-type oxide semiconductor. In contrast to polysilicon (band gap: 1.1 eV), this P-type oxide semiconductor has a band gap similar to that of the IGZO channel (2.5 to 3.0 eV). Consequently, it was confirmed through device simulation that there was no barrier due to the difference in band gaps, enabling the seamless supply of holes to the IGZO channel. Based on these results, we conducted a simulation to determine the optimal parameters for the P-type oxide semiconductor to be used as a filler, demonstrating improved erase operation when the P-type carrier density was 1019 cm−3 or higher and the band gap was 3.0 eV or higher.

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“…Although the usefulness of a vertical channel NAND (V-NAND) structure is clear, continuous improvement of device performance has been difficult because of several disadvantages of the polysilicon used as a channel material in realistic operating environments. The principal problems are an increase in the leakage current due to grain boundaries of the polysilicon, scattering of the threshold voltage, and a change in operating current with temperature [5][6][7][8]. Since these problems are fatal in V-NAND operation, research aimed at solving these problems is ongoing.…”

Section: Introductionmentioning

confidence: 99%

Floating Filler (FF) in an Indium Gallium Zinc Oxide (IGZO) Channel Improves the Erase Performance of Vertical Channel NAND Flash with a Cell-on-Peri (COP) Structure

Choi

Jeong

et al. 2021

Electronics

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In this study, we developed a V-NAND with an improved IGZO-P type (IP) floating filler (FF) structure based on an IGZO channel verified in previous studies and demonstrated that it has a very fast erase speed through device simulation. The proposed FF structure can supply holes generated through the Gate-Induced Drain Leakage (GIDL) phenomenon in the upper polysilicon string select line (SSL) channel to the IGZO channel through a P-type filler, and the structure proposed by this operation shows a very fast erase speed of 4 μs. A fast erase speed was achieved because the filler adjacent to the IGZO channel, like IP structures in previous studies, functioned as a path through which electrons emitted from the charge storage layer moved easily, rather than simply supplying holes. This assumption was confirmed by assessing the change in electron density of the channel during the erase operation. Next, we investigated the optimum conditions for leakage current reduction through various condition changes of the lower ground select line (GSL) gate in the proposed structure. We confirmed that the leakage current of the proposed structure can be minimized by changing the number of lower GSL gates, changing the length of the GSL channel, and/or changing the work function of the GSL gate material. We obtained a leakage current of 10−17 A when the GSL channel was 480 nm long with six GSL gates, each with a length of 40 nm. The work function of the gates was 4.96 eV.

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Statistical characterization of vertical poly-Si channel using charge pumping technique for 3D flash memory optimization

Cited by 11 publications

References 6 publications

An Improved Structure Enabling Hole Erase Operation When Using an IGZO Channel in a 3D NAND Flash Structure to Which COP (Cell-On-Peri) Structure Is Applied

An Improved Structure Enabling Hole Erase Operation When Using an IGZO Channel in a 3D NAND Flash Structure to Which COP (Cell-On-Peri) Structure Is Applied

An Optimized Device Structure with Improved Erase Operation within the Indium Gallium Zinc Oxide Channel in Three-Dimensional NAND Flash Applications

Floating Filler (FF) in an Indium Gallium Zinc Oxide (IGZO) Channel Improves the Erase Performance of Vertical Channel NAND Flash with a Cell-on-Peri (COP) Structure

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