We investigated the impact of the passivation layer on the stability of indium-gallium-zinc oxide (IGZO) thin film transistors. While the device without any passivation layer showed a huge threshold voltage (Vth) shift under positive gate voltage stress, the suitably passivated device did not exhibit any Vth shift. The charge trapping model, which has been believed to be a plausible mechanism, cannot by itself explain this behavior. Instead, the Vth instability was attributed to the interaction between the exposed IGZO backsurface and oxygen and/or water in the ambient atmosphere during the gate voltage stress.

The effect of water exposure on amorphous indium-gallium-zinc oxide ͑a-IGZO͒ semiconductors was reported. It was found that water can diffuse in and out of the a-IGZO film, reversibly affecting the transistor properties. Two competing mechanisms depending on the thickness of the active channel were clarified. The electron donation effect caused by water adsorption dominated for the thicker a-IGZO films ͑ജ100 nm͒, which was manifested in the large negative shift ͑Ͼ14 V͒ of the threshold voltage. However, in the case of the thinner a-IGZO films ͑ഛ70 nm͒, the dominance of the water-induced acceptorlike trap behavior was observed. The direct evidence for this behavior was that the subthreshold swing was greatly deteriorated from 0.18 V/decade ͑before water exposure͒ to 4.4 V/decade ͑after water exposure͒ for the thinnest a-IGZO films ͑30 nm͒. These results can be well explained by the screening effect of the intrinsic bulk traps of the a-IGZO semiconductor.

The authors report the fabrication of high performance thin film transistors (TFTs) with an amorphous indium gallium zinc oxide (a-IGZO) channel, which was deposited by cosputtering using a dual IGZO and indium zinc oxide (IZO) target. The effect of the indium content on the device performance of the a-IGZO TFTs was investigated. At a relatively low IZO power of 400W, the field-effect mobility (μFE) and subthreshold gate swing (S) of the a-IGZO TFTs were dramatically improved to 19.3cm2∕Vs and 0.35V/decade, respectively, compared to those (11.2cm2∕Vs and 1.11V/decade) for the TFTs with the a-IGZO channel (reference sample) prepared using only the IGZO target. The enhancement in the subthreshold IDS-VGS characteristics at an IZO power of 400W compared to those of the reference sample was attributed to the reduction of the interface trap density rather than the reduction of the bulk defects of the a-IGZO channel.

The effect of Ar plasma treatment on amorphous indium gallium zinc oxide (a-IGZO) thin films was investigated. The net electron carrier concentration (1020–1021cm−3) of the a-IGZO thin films dramatically increased upon their exposure to the Ar plasma compared to that (1014cm−3) of the as-deposited thin film. The authors attempted to reduce the contact resistance between the Pt∕Ti (source/drain electrode) and a-IGZO (channel) by using the Ar plasma treatment. Without the treatment, the a-IGZO thin film transistors (TFTs) with W∕L=50∕4μm exhibited a moderate field-effect mobility (μFE) of 3.3cm2∕Vs, subthreshold gate swing (S) of 0.25V∕decade, and Ion∕off ratio of 4×107. The device performance of the a-IGZO TFTs was significantly improved by the Ar plasma treatment. As a result, an excellent S value of 0.19V∕decade and high Ion∕off ratio of 1×108, as well as a high μFE of 9.1cm2∕Vs, were achieved for the treated a-IGZO TFTs.

The authors report on the fabrication of thin film transistors (TFTs), which use an amorphous indium gallium zinc oxide (a-IGZO) channel, by rf sputtering at room temperature and for which the channel length and width are patterned by photolithography and dry etching. To prevent plasma damage to the active channel, a 100-nm-thick SiOx layer deposited by plasma enhanced chemical vapor deposition was adopted as an etch stopper structure. The a-IGZO TFT (W∕L=10μm∕50μm) fabricated on glass exhibited a high field-effect mobility of 35.8cm2∕Vs, a subthreshold gate swing value of 0.59V∕decade, a thrseshold voltage of 5.9V, and an Ion∕off ratio of 4.9×106, which is acceptable for use as the switching transistor of an active-matrix TFT backplane.

Carbon nanotube transistors exhibiting high on-state conductance, carrier mobilities, and on−off ratios are achieved using polymer electrolytes as gate media. Nearly ideal gate efficiencies allow operation at very small voltages without the commonly observed problem of hysteresis in back-gated nanotube and nanowire transistors. By varying the electron donating and accepting ability of the chemical groups of the host polymer, unipolar p or n devices or ambipolar transistors that are stable at room temperature in air are also shown to be easily fabricated. With simple methods such as spin casting of polymer films, high-performance polymer electrolyte-gated nanotube transistors may provide useful components for and an alternative route to developing hybrid electronics.

The purpose of this paper is to give an overview of the state-of-the-art of metal oxide thin-film transistors (TFTs). First, the question of how to achieve high-performance oxide TFTs is addressed, including the exploration of new channel materials, the realization of low-resistance ohmic contacts and the implementation of high-k dielectric materials as the gate insulator. The electrical instability of the oxide TFTs is also discussed, which is critical for their application in flexible backplane electronics: special attention is given to the understanding of the degradation mechanism of oxide TFTs against bias thermal stress (BTS) and light illuminated BTS. Finally, the recent application of oxide TFTs in active matrix displays, such as electronic paper, liquid crystal displays and organic light-emitting diodes, is addressed.

We investigated the impact of photon irradiation on the stability of gallium-indium-zinc oxide (GIZO) thin film transistors. The application of light on the negative bias temperature stress (NBTS) accelerated the negative displacement of the threshold voltage (Vth). This phenomenon can be attributed to the trapping of the photon-induced carriers into the gate dielectric/channel interface or the gate dielectric bulk. Interestingly, the negative Vth shift under photon-enhanced NBTS condition worsened in relatively humid environments. It is suggested that moisture is a significant parameter that induces the degradation of bias-stressed GIZO transistors.