We investigated the impact of photon irradiation on the stability of gallium-indium-zinc oxide (GIZO) thin film transistors. The application of light on the negative bias temperature stress (NBTS) accelerated the negative displacement of the threshold voltage (Vth). This phenomenon can be attributed to the trapping of the photon-induced carriers into the gate dielectric/channel interface or the gate dielectric bulk. Interestingly, the negative Vth shift under photon-enhanced NBTS condition worsened in relatively humid environments. It is suggested that moisture is a significant parameter that induces the degradation of bias-stressed GIZO transistors.

This study examined the effect of gate dielectric materials on the light-induced bias instability of Hf-In-Zn-O ͑HIZO͒ transistor. The HfO x and SiN x gated devices suffered from a huge negative threshold voltage ͑V th ͒ shift ͑Ͼ11 V͒ during the application of negative-bias-thermal illumination stress for 3 h. In contrast, the HIZO transistor exhibited much better stability ͑Ͻ2.0 V͒ in terms of V th movement under identical stress conditions. Based on the experimental results, we propose a plausible degradation model for the trapping of the photocreated hole carrier either at the channel/ gate dielectric or dielectric bulk layer.

We investigated the effect of device configuration on the light-induced negative bias thermal instability of gallium indium zinc oxide transistors. The V th of back-channel-etch ͑BCE͒-type transistors shifted by Ϫ3.5 V, and the subthreshold gate swing ͑SS͒ increased from 0.88 to 1.38 V/decade after negative bias illumination temperature stress for 3 h. However, etch-stopper-type devices exhibited small V th shifts of Ϫ0.8 V without degradation in the SS value. It is believed that the inferior instability of the BCE device is associated with the formation of an interfacial molybdenum ͑Mo͒ oxychloride layer, which occurs in the course of dry etching Mo using Cl 2 /O 2 for source/drain patterning.

The threshold voltage instability ͑V th ͒ in indium-gallium-zinc oxide thin film transistor was investigated with disparate SiN x gate insulators under bias-temperature-illumination stress. As SiN x film stress became more tensile, the negative shift in V th decreased significantly from Ϫ14.34 to Ϫ6.37 V. The compressive films exhibit a nitrogen-rich phase, higher hydrogen contents, and higher N-H bonds than tensile films. This suggests that the higher N-H related traps may play a dominant role in the degradation of the devices, which may provide and/or generate charge trapping sites in interfaces and/or SiN x insulators. It is anticipated that the appropriate optimization of gate insulator properties will help to improve device reliability.

In this study, we examine the possibility of using Ti/Cu bilayer as source/drain electrodes for SiNx-passivated Hf–In–Zn–O (HIZO) thin film transistors by comparing their electrical properties with devices that use Mo electrodes. The Mo devices operate in depletion mode with a higher field effect mobility, while the Ti/Cu devices exhibit an improved subthreshold swing and operate in enhancement mode. Transmission electron microscopy characterization reveals the formation of an amorphous TiOx layer at the Ti/HIZO interface, which is suggested to be responsible for the disparate device characteristics in terms of contact resistance and threshold delay.