Analysis of photodepopulation of electron traps in HfO2 films grown by atomic layer deposition is shown to provide the trap energy distribution across the entire oxide bandgap. The presence is revealed of two kinds of deep electron traps energetically distributed at around Et ≈ 2.0 eV and Et ≈ 3.0 eV below the oxide conduction band. Comparison of the trapped electron energy distributions in HfO2 layers prepared using different precursors or subjected to thermal treatment suggests that these centers are intrinsic in origin. However, the common assumption that these would implicate O vacancies cannot explain the charging behavior of HfO2, suggesting that alternative defect models should be considered.
TANOS endurance is mainly governed by interface traps at the substrate-tunnel oxide interface, generated upon electrical stress, rather than by fixed charge in the tunnel oxide/blocking dielectric or by incomplete charge compensation in the nitride. As a result of acceptor resp. donor trap formation in the upper resp. lower half of the Si band gap, the V th program/erase window monotonically shifts upward whereas the V fb window exhibits turn-around behavior. Interface trap generation rate is highest during the erase operation and depends also on the memory stack process. Introduction TANOS charge trap Flash (CTF) with SiO 2 -Si 3 N 4 -Al 2 O 3 memory stack and TaN metal gate is a candidate technology to replace conventional floating gate technology for multilevel NAND applications beyond the 32nm node. Whereas a lot of effort is dedicated to improvement of erase performance and retention [1] much less attention is paid to TA-NOS endurance. In conventional floating gate (FG) NAND technology both the program and erase operations proceed by electron tunneling to and from the FG. In contrast, TA-NOS erase occurs mainly through holes tunneling from the substrate [2]. As a result, the degradation mechanisms governing endurance are likely different for the latter technology. A detailed analysis of TANOS program/erase (P/E) window instability upon cycling is the subject of this paper.
Results & discussionANO stacks were processed on 300mm wafers with fixed 4nm ISSG bottom oxide, 5nm PECVD nitride, and 10nm ALD Al 2 O 3 using H 2 O precursor. Variations on these reference conditions were part of the experiment. PVD-TaN inserted polysilicon was used as gate material. Characterization was done partly on capacitors with extra n+junction by monitoring with high-frequency C-V the flatband shift ΔV fb as well as threshold voltage shift ΔV th with respect to the initial value, partly on cells by ΔV th . In addition, charge pumping was done on the cells to monitor interface traps. Fig. 1 shows typical cell P/E window as function of cycle count. At low cycle count there is a slight increase of the erased level mainly, indicative for trapped negative charge in the stack [3]. At high cycle count both the programmed and erased V th go up at much higher rate. The window shift accumulates to several Volts at the highest cycle counts. To interpret this behavior, Fig. 2a presents the full I-V characteristics in programmed and erased state, respectively, recorded at selected cycle counts. P/E V th shift is the net result of two contributions: (1) a shift over the voltage axis from variation in fixed charge in the stack (2) a decrease of subthreshold slope as well as transconductance, Fig. 2b, from trap generation at the substrate/tunnel oxide interface. The latter contribution causes the P/E window shift to depend on the current level at which V th is monitored. The generation of interface traps is confirmed by charge pumping (CP) in Fig. 3. From fresh to 10kcycles, CP current I cp , which is proportional to interface trap density N it ...
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