Two-Pulse $C$–$V$ : A New Method for Characterizing Electron Traps in the Bulk of $ \hbox{SiO}_{2}/\hbox{high-}\kappa$ Dielectric Stacks

Optimization of inter-gate-dielectrics in hybrid float gate devices to reduce window instability during memory operations

“…Since there are a large number of electron traps in the high-k IGD layer [4][5][6][7]10], electron redistribution between FG and IGD and/or between IGD and CG could introduce window instability. Fig.…”

“…However, It is well known that the electron trap density in high-k materials is a few orders of magnitude higher than that in SiO 2 [4,5]. Efforts have been made to investigate the properties of these traps and the impact of their trapping/detrapping on memory operations [6][7][8][9][10]. Various window shifts during memory retention and endurance, read/pass disturbance operations in IGD-only or the conventional poly-Si FG cells have been observed and attributed to electron trapping/detrapping in the high-k stacks [11][12][13].…”

Characterisation of electron traps in high-k dielectric stacks for Flash memory applications using fast pulse techniques

“…After the electron traps are filled under a positive gate bias, a given V discharge is applied and only electron traps with energy level higher than the silicon conduction band bottom can be discharged via tunneling [4], since there are little empty states in the silicon band gap. If a gate bias gives the corresponding potential drop of V SiO2 across the SiO 2 layer, the energy level of electron traps will change by  IL = qV SiO2 in the high-κ layer at the SiO 2 /high-κ interface and by  G = qV dielectric at the gate interface, as illustrated in Fig.1.…”

“…Apart from the conventional charge-pumping, highfrequency C-V and Id-Vg techniques, several new techniques have been developed recently to investigate the energy and spatial distributions of electron trap in thick high-κ layers for Flash memory applications, such as the fast 2-pulse and multi-pulse techniques [4]- [7] and the charge injection and sensing techniques [3]. Various window shifts during memory operations have been observed and explained by electron trapping/detrapping in high-k stacks [3]- [7].…”

“…In this paper, several pulse techniques will be compared and are applied to characterise the defects in high-κ stacks for Flash memory applications. Several V TH /V FB measurement techniques with different measurement times have been used in this work, including pulsed C-V (PCV) [4]- [5], pulsed I-V (PIV) [6]- [7], and their corresponding measurement times are 500 µs and 5 µs, respectively. The shift of threshold voltage in MOS transistors, V TH , is measured at a constant drain current of 5×10 -5 A and a drain bias of 100 mV.…”