Characterisation of electron traps in high-k dielectric stacks for Flash memory applications using fast pulse techniques

Abstract

High-κ dielectric stacks have been used to replace the conventional SiO 2 -based dielectric stacks in Flash memory cells in the 20 nm technology generation. The electron trap density in high-κ layers is orders of magnitude higher than that in SiO 2 , which introduces fast transient trapping/detrapping and affects the program/erase, retention and endurance of memory cells. Several fast pulse techniques have been developed to characterize electron traps throughout the dielectric stack, including 2-pulse and multi-pulse C-V and I-V techniques. These techniques are compared in this work and electron trapping in the high-κ stacks and its impact on memory cell performances are evaluated using these techniques.