VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices

Govoreanu, B.; Blomme, Pieter; Rosmeulen, M.; Houdt, J. Van; Meyer, K. De

doi:10.1109/led.2002.807694

Cited by 178 publications

(87 citation statements)

References 12 publications

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“…20 In order to ensure high tunnel transparency and low thermionic current at moderate electrical fields, different crested barrier designs were investigated. 4,21 These designs aim to achieve an engineered variable oxide thickness (VARIOT) dielectric to optimize tunnel current. 21 By alternating the same ALD recipes of Al 2 O 3 and HfO 2 , we have achieved the crested structures composed of sandwiched layers of Al 2 O 3 and HfO 2 as described in Fig.…”

Section: Crested Barrier Engineeringmentioning

confidence: 99%

Highly transparent low capacitance plasma enhanced atomic layer deposition Al2O3-HfO2 tunnel junction engineering

Hajjam¹,

Baboux²,

Calmon

et al. 2013

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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The development of metallic single electron transistor (SET) depends on the downscaling and the electrical properties of its tunnel junctions. These tunnel junctions should insure high tunnel current levels, low thermionic current, and low capacitance. The authors use atomic layer deposition to fabricate Al2O3 and HfO2 thin layers. Tunnel barrier engineering allows the achievement of low capacitance Al2O3 and HfO2 tunnel junctions using optimized annealing and plasma exposure conditions. Different stacks were designed and fabricated to increase the transparency of the tunnel junction while minimizing thermionic current. This tunnel junction is meant to be integrated in SET to enhance its electrical properties (e.g., operating temperature, ION/IOFF ratio).

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Section: Crested Barrier Engineeringmentioning

confidence: 99%

Highly transparent low capacitance plasma enhanced atomic layer deposition Al2O3-HfO2 tunnel junction engineering

Hajjam¹,

Baboux²,

Calmon

et al. 2013

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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“…To enable scaling, the SiO 2 tunnel layer is often replaced by a composite multilayered stack [12]- [18]. The engineering of the tunnel dielectric with crested [13], VARIOT [14], symmetric composite [15] tunnel barrier, and double quantum-barrier structure [16] was also found to improve performance. However, the use of thin multilayer deposited tunnel dielectric may compromise the overall cell reliability, particularly for multilevel cell (MLC) operation which requires high P/E voltages for large MW, resulting in degraded P/E cycling endurance capability.…”

Section: Introductionmentioning

confidence: 99%

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Sandhya

Oak

Chattar

et al. 2009

IEEE Trans. Electron Devices

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Abstract-Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge loss remain the challenging issues for charge trap Flash (CTF) memories. In this paper, the dependence of SANOS memory performance and reliability on the composition of silicon nitride (SiN) layer is extensively studied. The effect of varying the Si:N ratio on program (P)/E and retention characteristics is investigated. SiN composition is shown to significantly alter the electron and hole trap properties. Varying the SiN composition from N-rich (N + ) to Si-rich (Si + ) lowers electron trap depth but increases hole trap depth, causing lower P state saturation but significant overerase, resulting in an enhanced memory window. During retention, P state charge loss depends on thermal emission followed by the tunneling out of electrons mostly through tunnel dielectric, which becomes worse for Si + SiN. Erase state charge loss mainly depends on hole redistribution under the influence of internal electric fields, which improves with Si + SiN. This paper identifies several important performances versus reliability tradeoffs to be considered during the optimization of SiN layer composition. It also explores the option for CTF optimization through the engineering of SiN stoichiometry for multilevel cell NAND Flash applications.Index Terms-Charge trap Flash (CTF), program/erase (P/E) window, retention, SANOS, silicon nitride (SiN), SONOS.

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“…For 6 nm SiO 2 thickness, the program potential drop at the floating gate is extracted as 4.8 V and for 8 nm SiO 2 thickness, the retention potential drop is extracted as 3.2 V, which is near to 3.6 V computed in Ref. 11. For simplicity, another feature that can be used to assess the performance of VARIOT is the slope of the J-V curve.…”

Section: Device Characterization Of Gaa-fg With Variot Tunnel Layermentioning

confidence: 80%

“…Additionally, as far as this work is concerned, currently there are no known solution to significantly scale the SiO 2 tunnel layer below 6 nm 30) and therefore, can be set as a benchmark for fast program operation. To program a memory cell for a given V prog requires gate current in the order of J prog ≈ ΔV T · C IPD =t prog 11) and to obtain a good separation between two memory states, the threshold voltage shift (ΔV T ) must be at least 3 V, 11) where for 6 nm SiO 2 depicts at approximately programming time (t prog ) of 100 µs shown by red-dashed line of Fig. 6.…”

Section: Simulation Validation Of Gaa-fgmentioning

confidence: 99%

“…[3][4][5][6][7]10) In addition, it also suffers from poor retention due to the charge-trapped around the triangular corners. To compensate both the programming time and data retention of GAA-FG, in this work, the tunnel barrier engineering concept of variable oxide thickness (VARIOT) [11][12][13][14][15][16] as tunnel layer is utilized. It has been previously studied for charge-trapping 15,16) and even for hybrid floating [17][18][19] gate devices and its performances as tunnel oxide layer for 3D FG cell is yet to be unveiled.…”

Section: Introductionmentioning

confidence: 99%

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Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Hamzah

Alias

Ismail

2018

Jpn. J. Appl. Phys.

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The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si 3 N 4 , Al 2 O 3 , HfO 2 , and ZrO 2 ) with low-k SiO 2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/ high-k barrier-stacked and extracting their Fowler-Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO 2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO 2 has been obtained using SiO 2 / Al 2 O 3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of %3.6/3.6 V gate stress.

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VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices

Cited by 178 publications

References 12 publications

Highly transparent low capacitance plasma enhanced atomic layer deposition Al2O3-HfO2 tunnel junction engineering

Highly transparent low capacitance plasma enhanced atomic layer deposition Al2O3-HfO2 tunnel junction engineering

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

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