Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Abstract

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si 3 N 4 , Al 2 O 3 , HfO 2 , and ZrO 2 ) with low-k SiO 2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/ high-k barrier-stacked and extracting their Fowler-Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO 2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO 2 has been obtained using SiO 2 / Al 2 O 3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of %3.6/3.6 V gate stress.

Reliability of graphene as charge storage layer in floating gate flash memory

“…In part 1, using Silvaco TCAD Tools, the virtual device structure of graphene-based FG non-volatile memory cell is simulated based on experimental work in [6], refer Table 1 and Figure 2 while the graphene properties parameters are referred to [11]. The FN tunnelling model is used as the electron tunnelling through a barrier using the extracted FN parameters work in [12]. The number of electrons stored in FG and memory window for 1s from the simulation is validated with experimental data [6] refer Figure 4.…”

“…Variable Programming Erasing FN tunneling coefficients [12] AFN (A/V 2 ) 1.23 × 10 −6 1.87 × 10 −7 BFN (V/cm) 2.37 × 10 8 1.88 × 10 8 BBHE tunneling coefficients [13] BBA (cm -1 V -2 s -1 ) 9.6615 × 10 18 -BBB (V/cm) 3.0 × 10 7 -BBγ 2.0 -For part 2, the simulation works continue by changing the doping type of flash memory cells from nchannel to p-channel (refer Table 1) while all the cell dimensions and parameters remain unchanged (refer Figure 3). The device fabrication for flash MLG device in [6] did not mentioned the exact gate length of the device therefore 600 nm gate length is chosen for simulation due to the standard simulation value for MOSFET.…”

“…The device fabrication for flash MLG device in [6] did not mentioned the exact gate length of the device therefore 600 nm gate length is chosen for simulation due to the standard simulation value for MOSFET. For P/E operations, BBHE and FN tunnelling model was operated to capture the electrons tunnelling through tunnel oxide using the BBHE and FN coefficients that were initially extracted from the optimization work in [12,13] (refer Table 2). BBHE tunnelling is applied for programming in p-channel flash memory cell due to very poor current-voltage (I-V) characteristics if FN tunnelling is applied.…”

Molecular/Nanostructured Functional Metal Oxide Stacks for Nanoscale Nanosecond Information Storage

“…Note that tunneling oxide thicknesses of 8 nm or more are currently used in the commercial flash memory chips in order to meet the 10 years' data retention time requirement. [40] The utilized 5 nm SiO 2 tunneling barrier stretches slightly the 6 nm benchmark for fast programming operation [1,41] counterbalancing leakage by confinement on molecular states. The metal oxide stack utilizes two main functional components: the charge-trapping core and the optically active gate oxide cap.…”

N2 gas flow rate dependence on the high-k LaB x N y thin film characteristics formed by RF sputtering for floating-gate memory applications

“…[18][19][20][21][22][23] To improve the memory characteristics of the floating-gate devices, there are many reports to realize low-voltage operation utilizing high-k dielectrics. [24][25][26][27][28][29][30] We have reported the lowvoltage operation of the floating-gate structure utilizing a Ndoped LaB 6 /LaB x N y stacked structure. 10) Although the program/erase characteristics were observed, the memory characteristics should be improved.…”